Datasheet

TAS5548
SLES270 –NOVEMBER 2012 www.ti.com
11.6 Headphone Configuration Control Register (0x0D)
Bit D0 is don't care.
Table 11-6. Headphone Configuration Control Register Format
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 – – – – – – – Disable back-end reset sequence for Headphone
1 – – – – – – – Enable back-end reset sequence for Headphone
– 0 – – – – – – Valid is high when headphone PWM outputs are switching
– 1 – – – – – – Valid low in Headphone mode.
– – 0 – – – – – Reserved
– – 1 – – – – – Reserved
– – – 0 – – – – Reserved
– – – 1 – – – – Reserved
– – – – 0 – – – Reserved
– – – – 1 – – – Reserved
– – – – – 0 – – Reserved
– – – – – 1 – – Reserved
– – – – – – 0 – Reserved
– – – – – – 1 – Reserved
11.7 Serial Data Interface Control Register (0x0E)
Nine serial modes can be programmed via the I
2
C interface.
Table 11-7. Serial Data Interface Control Register Format for SDOUT and SDIN5
SERIAL DATA
WORD LENGTHS D3 D2 D1 D0
INTERFACE FORMAT
Right-justified 16 0 0 0 0
Right-justified 20 0 0 0 1
Right-justified 24 0 0 1 0
I
2
S 16 0 0 1 1
I
2
S 20 0 1 0 0
I
2
S 24 0 1 0 1
Left-justified 16 0 1 1 0
Left-justified 20 0 1 1 1
Left-justified 24 1 0 0 0
Illegal 1 0 0 1
Illegal 1 0 1 0
Illegal 1 0 1 1
Illegal 1 1 0 0
Illegal 1 1 0 1
Illegal 1 1 1 0
Illegal 1 1 1 1
11.8 Soft Mute Register (0x0F)
Do not use this register if using the remapped output mixer configuration.
78 Serial-Control Interface Register Definitions Copyright © 2012, Texas Instruments Incorporated
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