Datasheet

TAS5548
www.ti.com SLES270 –NOVEMBER 2012
TOTAL
I
2
C
REGISTER FIELDS DESCRIPTION OF CONTENTS DEFAULT STATE (hex)
BYTES
SUBADDRESS
Ch1–Ch7 , DRC1 slope k0 DRC1 slope (k0) 0040 0000 0FC0 0000 0F90 0000
0x9A 12 Ch1–Ch7, DRC1 slope k1 DRC1 slope (k1)
Ch1–Ch7 DRC1 slope k2 DRC1 slope (k2)
Ch1–Ch7 DRC1 offset 1 DRC1 offset 1 (O1) – 4 bytes FF82 3098 0195 B2C0
0x9B 8
Ch1–Ch7 DRC1 offset 2 DRC1 offset 2 (O2) – 4 bytes
Ch1–Ch7 DRC1 attack DRC1 attack 0000 883F 007F 77C0 0000 0056 003F FFA8
Ch1–Ch7 DRC1 (1 – attack) DRC1 (1 – attack)
0x9C 16
Ch1–Ch7 DRC1 decay DRC1 decay
Ch1–Ch7 DRC1 (1 – decay) DRC1 (1 – decay)
Ch8 DRC2 energy DRC2 energy 0000 883F 007F 77C0
0x9D 8
Ch8 DRC2 (1 – energy) DRC2 (1 – energy)
Ch8 DRC2 threshold T1 DRC2 threshold (T1) – 4 bytes 0B20 E2B2 06F9 DE58
0x9E 8
Ch8 DRC2 threshold T2 DRC2 threshold (T2) – 4 bytes
Ch8 DRC2 slope k0 DRC2 slope (k0) 0040 0000 0FC0 0000 0F90 0000
0x9F 12 Ch8 DRC2 slope k1 DRC2 slope (k1)
Ch8 DRC2 slope k2 DRC2 slope (k2)
Ch8 DRC2 offset 1 DRC2 offset (O1) – lower 4 bytes FF82 3098 0195 B2C0
0xA0 8
Ch8 DRC2 offset 2 DRC2 offset (O2) – lower 4 bytes
Ch8 DRC2 attack DRC 2 attack 0000 883F 007F 77C0 0000 0056 003F FFA8
Ch8 DRC2 (1 – attack) DRC2 (1 – attack)
0xA1 16
Ch8 DRC2 decay DRC2 decay
Ch8 DRC2 (1 – decay) DRC2 (1 – decay)
DRC bypass 1 Ch1 DRC1 bypass coefficient 0080 0000 0000 0000
0xA2 8
DRC inline 1 Ch1 DRC1 inline coefficient
DRC bypass 2 Ch2 DRC1 bypass coefficient 0080 0000 0000 0000
0xA3 8
DRC inline 2 Ch2 DRC1 inline coefficient
DRC bypass 3 Ch3 DRC1 bypass coefficient 0080 0000 0000 0000
0xA4 8
DRC inline 3 Ch3 DRC1 inline coefficient
DRC bypass 4 Ch4 DRC1 bypass coefficient 0080 0000 0000 0000
0xA5 8
DRC inline 4 Ch4 DRC1 inline coefficient
DRC bypass 5 Ch5 DRC1 bypass coefficient 0080 0000 0000 0000
0xA6 8
DRC inline 5 Ch5 DRC1 inline coefficient
DRC bypass 6 Ch6 DRC1 bypass coefficient 0080 0000 0000 0000
0xA7 8
DRC inline 6 Ch6 DRC1 inline coefficient
DRC bypass 7 Ch7 DRC1 bypass coefficient 0080 0000 0000 0000
0xA8 8
DRC inline 7 Ch7 DRC1 inline coefficient
DRC2 bypass 8 Ch8 DRC2 bypass coefficient 0080 0000 0000 0000
0xA9 8
DRC2 inline 8 Ch8 DRC2 inline coefficient
0xAA 8 Output Select and Mix to See 80 2nd Byte – Other 00
(8x2) PWM1
0xAB 8 Output Select and Mix to See 10 80 1st Two Bytes – Other 00
(8x2) PWM2
0xAC 8 Output Select and Mix to See 20 80 1st Two Bytes – Other 00
(8x2) PWM3
0xAD 8 Output Select and Mix to See 30 80 1st Two Bytes – Other 00
(8x2) PWM4
0xAE 8 Output Select and Mix to See 40 80 1st Two Bytes – Other 00
(8x2) PWM5
0xAF 8 Output Select and Mix to See 50 80 1st Two Bytes – Other 00
(8x2) PWM6
0xB0 12 Output Select and Mix to See 60 80 1st Two Bytes – Other 00
(8x3) PWM7
0xB1 12 Output Select and Mix to See 70 80 1st Two Bytes – Other 00
(8x3) PWM8
Copyright © 2012, Texas Instruments Incorporated 71
Serial-Control I
2
C Register Summary
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