Datasheet

CLK_Gen
Control
LRCK1
SCK1
SDIN1
SDIN2
8ch PWM
Modulator
+
HP-PWMOUT
32kHz–192kHz Input
4ch ASRC
Fixed 96kHz Output
32 bits Data Path
48 bits Accumulator
1365 Cycles
Fixed Processing DAP
10 Channel Input Mixer
8 Channel Processing
8 Channel Output Mixer
32kHz–192kHz Input
4ch ASRC
Fixed 96kHz Output
Serial Audio
Receiver
4ch
2 Stereo
Serial Audio
Receiver
4ch
2 Stereo
LRCKO/LRCKIN2
SCKO/SCKIN2
SDIN3
SDIN4
4ch
4ch
Serial Audio
Receiver
Transmitter
1 Stereo
SDOUT/SDIN5
I/
O
I
O
I
I
I
I
I
I/
O
I/
O
MCLKO/PSVC
OSC
12.288MHz
8ch
O
O
O
O
O
O
O
O
O
IO
2ch
2ch
Bypass mode
2ch
HPPWM
PWM8
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
TAS5548
www.ti.com SLES270 –NOVEMBER 2012
9.2 Serial Port Master/Slave Configurations
The inputs to the Digital Audio Processor (DAP) come from the Asynchronous Sample Rate Converter
block as follows:
Figure 9-3. Digital Audio Signal Flow Block Diagram
The DAP can feed audio data to and from the Serial Audio ports in the following manner. There are 3
main use cases:
1. Use Case 1: External Karaoke Microphone Input (ADC in on SDIN5) or External I2S Subwoofer
(a) SDIN1 through 4 are slave to an external source (such as a media decoder IC).
(b) A separate DOUT (for Sub) or Microphone Inout (SDIN5) needs to function at the post-ASRC rate.
(c) Therefore, the device is configured to use MCLKO, SCLKO and LRCLKO.
2. Use Case 2: Mixing two different data sources (e.g. Stereo Bluetooth I2S and CD/Media Decoder
(a) In an example where two different data sources need mixing, SDIN1/2 run at a different rate than
SDIN3/4
(b) SCLKIN-2 and LRCLKIN-2 are used to provide an LRCLK and SCLK for the second data
synchronous data source.
(c) DOUT (for a wireless sub) cannot be used in this mode, as no MCLKO, SCLKO or LRCLKO are
available.
3. Use Case 3: Creating an external loop for processing (e.g. using a TAS3108 or TAS3152 I2S
processor)
(a) SDIN1/2 run with SCLK and LRCLK as a slave.
(b) SDOUT acts as a "send for external processing", in master mode, synchronized to MLCKO,
SCLKO, LRCLKO
(c) SDIN3/4 Act as a "return from external processing", in master mode, synchronized to MLCKO,
SCLKO, LRCLKO
Copyright © 2012, Texas Instruments Incorporated Application Recommendations / Settings 65
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