Datasheet

A6 A0 ACK
Acknowledge
I CDevice Addressand
Read/WriteBit
2
R/WA6 A0 R/W ACK A0 ACK D7 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
LastDataByte
ACK
FirstDataByte
RepeatStart
Condition
Not
Acknowledge
I CDevice Addressand
Read/WriteBit
2
Subaddress OtherDataBytes
A7 A6 A5 D7 D0 ACK
Acknowledge
D7 D0
T0036-04
A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress DataByte
D7 D6 D1 D0 ACK
I CDevice Addressand
Read/WriteBit
2
Not
Acknowledge
R/WA1 A1
RepeatStart
Condition
T0036-03
TAS5548
SLES270 –NOVEMBER 2012 www.ti.com
8.6 Single-Byte Read
As shown in Figure 8-4, a single-byte, data-read transfer begins with the master device transmitting a start
condition followed by the I
2
C device address and the read/write bit. For the data-read transfer, both a write
and then a read are actually performed. Initially, a write is performed to transfer the address byte or bytes
of the internal memory address to be read. As a result, the read/write bit is a 0. After receiving the
TAS5548 address and the read/write bit, the TAS5548 responds with an acknowledge bit. In addition, after
sending the internal memory address byte or bytes, the master device transmits another start condition
followed by the TAS5548 address and the read/write bit again. This time the read/write bit is a 1,
indicating a read transfer. After receiving the TAS5548 address and the read/write bit, the TAS5548 again
responds with an acknowledge bit. Next, the TAS5548 transmits the data byte from the memory address
being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a
stop condition to complete the single-byte, data-read transfer.
Figure 8-4. Single-Byte Read Transfer
8.7 Multiple-Byte Read
A multiple-byte, data-read transfer is identical to a single-byte, data-read transfer except that multiple data
bytes are transmitted by the TAS5548 to the master device, as shown in Figure 8-5. Except for the last
data byte, the master device responds with an acknowledge bit after receiving each data byte.
Figure 8-5. Multiple-Byte Read Transfer
62 Copyright © 2012, Texas Instruments Incorporated
I
2
C Serial-Control Interface (Slave Addresses 0x36)
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