Datasheet

D7 D0 ACK
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress LastDataByte
A6 A5 A1 A0 R/W ACK A7 A5 A1 A0 ACK D7 ACK
Start
Condition
Acknowledge Acknowledge Acknowledge
FirstDataByte
A4 A3A6
OtherDataBytes
ACK
Acknowledge
D0 D7 D0
T0036-02
TAS5548
www.ti.com SLES270 –NOVEMBER 2012
8.4 Multiple-Byte Write
A multiple-byte, data-write transfer is identical to a single-byte, data-write transfer except that multiple data
bytes are transmitted by the master device to TAS5548, as shown in Figure 8-3. After receiving each data
byte, the TAS5548 responds with an acknowledge bit.
Figure 8-3. Multiple-Byte Write Transfer
8.5 Incremental Multiple-Byte Write
The I
2
C supports a special mode which permits I
2
C write operations to be broken up into multiple data
write operations that are multiples of four data bytes. These are 6-byte, 10-byte, 14-byte, 18-byte, etc.,
write operations that are composed of a device address, read/write bit, subaddress, and any multiple of
four bytes of data. This permits the system to write large register values incrementally without blocking
other I
2
C transactions.
This feature is enabled by the append subaddress function in the TAS5548. This function enables the
TAS5548 to append four bytes of data to a register that was opened by a previous I
2
C register write
operation but has not received its complete number of data bytes. Because the length of the long registers
is a multiple of four bytes, using four-byte transfers has only an integral number of append operations.
When the correct number of bytes has been received, the TAS5548 begins processing the data.
The procedure to perform an incremental multibyte-write operation is as follows:
1. Start a normal I
2
C write operation by sending the device address, write bit, register subaddress, and
the first four bytes of the data to be written. At the end of that sequence, send a stop condition. At this
point, the register has been opened and accepts the remaining data that is sent by writing four-byte
blocks of data to the append subaddress (0xFE).
2. At a later time, one or more append data transfers are performed to incrementally transfer the
remaining number of bytes in sequential order to complete the register write operation. Each of these
append operations is composed of the device address, write bit, append subaddress (0xFE), and four
bytes of data followed by a stop condition.
3. The operation is terminated due to an error condition, and the data is flushed:
(a) If a new subaddress is written to the TAS5548 before the correct number of bytes are written.
(b) If more or fewer than four bytes are data written at the beginning or during any of the append
operations.
(c) If a read bit is sent.
Copyright © 2012, Texas Instruments Incorporated 61
I
2
C Serial-Control Interface (Slave Addresses 0x36)
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