Datasheet

A6 A5 A4 A3 A2 A1 A0
R/W
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress DataByte
T0036-01
TAS5548
SLES270 –NOVEMBER 2012 www.ti.com
8.2 Single- and Multiple-Byte Transfers
The serial-control interface supports both single-byte and multiple-byte read/write operations for status
registers and the general control registers associated with the PWM. However, for the DAP data
processing registers, the serial-control interface supports only multiple-byte (four-byte) read/write
operations.
During multiple-byte read operations, the TAS5548 responds with data, a byte at a time, starting at the
subaddress assigned, as long as the master device continues to respond with acknowledges. If a
particular subaddress does not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the TAS5548 compares the number of bytes transmitted to the
number of bytes that are required for each specific subaddress. If a write command is received for a
biquad subaddress, the TAS5548 expects to receive five 32-bit words. If fewer than five 32-bit data words
have been received when a stop command (or another start command) is received, the data received is
discarded. Similarly, if a write command is received for a mixer coefficient, the TAS5548 expects to
receive one 32-bit word.
Supplying a subaddress for each subaddress transaction is referred to as random I
2
C addressing. The
TAS5548 also supports sequential I
2
C addressing. For write transactions, if a subaddress is issued
followed by data for that subaddress and the 15 subaddresses that follow, a sequential I
2
C write
transaction has taken place, and the data for all 16 subaddresses is successfully received by the
TAS5548. For I
2
C sequential write transactions, the subaddress then serves as the start address and the
amount of data subsequently transmitted, before a stop or start is transmitted, determines how many
subaddresses are written. As is true for random addressing, sequential addressing requires that a
complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data
for the last subaddress is discarded. However, all other data written is accepted; only the incomplete data
is discarded.
8.3 Single-Byte Write
As shown in Figure 8-2, a single-byte, data-write transfer begins with the master device transmitting a start
condition followed by the I
2
C device address and the read/write bit. The read/write bit determines the
direction of the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct
I
2
C device address and the read/write bit, the TAS5548 device responds with an acknowledge bit. Next,
the master transmits the address byte or bytes corresponding to the TAS5548 internal memory address
being accessed. After receiving the address byte, the TAS5548 again responds with an acknowledge bit.
Next, the master device transmits the data byte to be written to the memory address being accessed. After
receiving the data byte, the TAS5548 again responds with an acknowledge bit. Finally, the master device
transmits a stop condition to complete the single-byte, data-write transfer.
Figure 8-2. Single-Byte Write Transfer
60 Copyright © 2012, Texas Instruments Incorporated
I
2
C Serial-Control Interface (Slave Addresses 0x36)
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