Datasheet

7-BitSlave Address
R/
W
8-BitRegister Address(N)
A
8-BitRegisterDataFor
Address(N)
Start Stop
SDA
SCL
7
6
5
4
3
2 1
0
7
6
5
4
3
2 1
0
7
6
5
4
3
2 1
0
7
6
5
4
3
2 1
0
A
8-BitRegisterDataFor
Address(N)
A A
T0035-01
TAS5548
www.ti.com SLES270 –NOVEMBER 2012
8 I
2
C Serial-Control Interface (Slave Addresses 0x36)
The TAS5548 has a bidirectional I
2
C interface that is compatible with the Inter-IC (I
2
C) bus protocol and
supports both 100-kbps and 400-kbps data transfer rates for single- and multiple-byte write and read
operations. This is a slave-only device that does not support a multimaster bus environment or wait state
insertion. The control interface is used to program the registers of the device and to read device status.
The TAS5548 supports the standard-mode I
2
C bus operation (100 kHz maximum) and the fast I
2
C bus
operation (400 kHz maximum). The TAS5548 performs all I
2
C operations without I
2
C wait cycles.
The I
2
C address is 0x36 if ASEL pin = '1, but if the value of the pin = '0', then respective values will be
0X34.
8.1 General I
2
C Operation
The I
2
C bus employs two signals—SDA (data) and SCL (clock)—to communicate between integrated
circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data can be
transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte
transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer
operation begins with the master device driving a start condition on the bus and ends with the master
device driving a stop condition on the bus. The bus uses transitions on SDA while the clock is high to
indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high
transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period.
These conditions are shown in Figure 8-1. The master generates the 7-bit slave address and the
read/write (R/W) bit to open communication with another device and then waits for an acknowledge
condition. The TAS5548 holds SDA low during the acknowledge clock period to indicate an
acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is
addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same
signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for
the SDA and SCL signals to set the high level for the bus.
Figure 8-1. Typical I
2
C Sequence
The number of bytes that can be transmitted between start and stop conditions is unlimited. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer
sequence is shown in Figure 8-1.
The 7-bit address for the TAS5548 is 0011011. When the R/W bit is added as the LSB, the I
2
C write
address is 0x36 and the I
2
C read address is 0x37.
Copyright © 2012, Texas Instruments Incorporated 59
I
2
C Serial-Control Interface (Slave Addresses 0x36)
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