Datasheet

TAS5548
SLES270 –NOVEMBER 2012 www.ti.com
7.11 10.6 LRCKO and SCLKO
There are output pins for LRCLK output and SCK output. As the SDIN5 rate (which always follow internal sample
rate) and the SDOUT rate (which is 44.1 kHz or 48 kHz) is different, the LRCLKO will be the internal sample rate
(96 kHz or 192 kHz) when SDIN5 is activated (SDOUT is not available) and it will be 44.1 kHz or 48 kHz when
SDOUT is available. The SCLKO will be always 64x LRCLKO.
8.5 Master Clock Output (MCLKO) Master clock is generated from the MCLK input itself in Non XTAL device and
from the XTAL in XTAL device. There is a clock divider with division factor of 4, 2 or 1 that can be selected from.
The default is no division
58 Electrical Specifications Copyright © 2012, Texas Instruments Incorporated
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