Datasheet

23
22
SCLK
32Clks
LRCLK
LeftChannel
24-BitMode
1
20-BitMode
16-BitMode
15
14
MSB LSB
SCLK
32Clks
RightChannel
2-ChannelRight-Justified(SonyFormat)StereoInput
T0034-03
19 18
1
19 18
1
0
0
0
15
14
15
14
23
22 1
15
14
MSB LSB
19 18
1
19 18
1
0
0
0
15
14
15
14
TAS5548
www.ti.com SLES270 –NOVEMBER 2012
7.8.3 Right-Justified Timing
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
64 f
S
is used to clock in the data. The first bit of data appears on the data lines eight bit-clock periods (for 24-bit
data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCLK
transitions. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5548 masks
unused leading data bit positions.
Figure 7-11. Right-Justified 64-f
S
Format
7.9 OUTPUT Serial Audio Output
Serial audio output formats supported are left justified (LJ), right justified (RJ) and I2S.
Serial audio output word lengths supported are 16 bits, 20 bits and 24 bits.
Other formats or word lengths are not supported.
7.10 10.5 I2S Master Mode
In master mode, the SDIN1/SDIN2/SDIN3/SDIN4 and optionally SDIN5 are assumed to be generated according
to LRCLK and SCLK output by TAS5548.
This is only useful when the ASRC is bypassed with XTAL device since with the ASRC in use the SDINs do not
have to follow LRCLK / SCLK output due to conversion by the ASRC. In this case, the internal sample rate, the
LRCLK output and the SCLK output will be generated using the XTAL. As the SDIN5 will never go through the
ASRC, the SDIN5 can be accepted with master mode only. Internally, the LRCLK and SCLK for the SDIN5 are
always assumed to be the same with LRCLK and SCLK outputs. When set in I2S master mode, the I2S
input/output formats should not mix I2S and LJ/RJ. If the input format is I2S then the output format must also be
I2S. When the input format is not I2S then the output format must also not be I2S. Left justified and right justified
can be mixed. When the SDIN5 is activated (SDOUT is not available), the LRCLKO will be the internal sample
rate, that is either 96 kHz or 192 kHz. The SCLKO will be 64x LRCLKO.
Copyright © 2012, Texas Instruments Incorporated Electrical Specifications 57
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