Datasheet

23
22
SCLK
32Clks
LRCLK(NoteReversedPhase)
LeftChannel
24-BitMode
1
19 18
20-BitMode
16-BitMode
15
14
MSB LSB
32Clks
RightChannel
2-ChannelI S(PhilipsFormat)StereoInput
2
T0034-01
5
4
9 8
1
0
0
4
5
1
0
23
22 1
19 18
15
14
MSB LSB
5
4
9 8
1
0
0
4
5
1
0
SCLK
TAS5548
www.ti.com SLES270 –NOVEMBER 2012
7.8 Serial Audio Interface Control and Timing
7.8.1 Input I
2
S Timing
I
2
S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 64 f
S
is used
to clock in the data. From the time the LRCLK signal changes state to the first bit of data on the data lines is a
delay of one bit clock. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5548
masks unused trailing data bit positions.
Figure 7-9. I
2
S 64-f
S
Format
Copyright © 2012, Texas Instruments Incorporated Electrical Specifications 55
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