Datasheet

PDN
VALID
t
su
t
p(DMSTATE)
< 300 µs
T0030-03
t
w(RESET)
Earliest time
that PWM outputs
could be enabled
RESET
VALID
t
r
(DMSTATE)
370 ns
t
r (I2C_ready)
Determine SCLK rate
and MCLK ratio. Enable via I
2
C.
T0029-04
TAS5548
SLES270 –NOVEMBER 2012 www.ti.com
7.7.4 Reset Timing (RESET)
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
t
r(DMSTATE)
Time to Non PWM Switching low 400 ns
t
w(RESET)
Pulse duration, RESET active 400 None ns
t
r(I2C_ready)
Time to enable I
2
C 5 ms
NOTE: Since a crystal time base is used, the system determines the CLK rates. Once the data rate and master clock ratio is
determined, the system outputs audio if a master volume command is issued.
Figure 7-4. Reset Timing
7.7.5 Power-Down (PDN) Timing
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
t
p(DMSTATE)
Time to Non PWM Switching low 650 μs
Number of MCLKs preceding the release of PDN 5
t
su
Device startup time 200 µs
Time to audio output 160 mS
Figure 7-5. Power-Down Timing
52 Electrical Specifications Copyright © 2012, Texas Instruments Incorporated
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