Datasheet

t
h1
t
su1
t
su2
t
h2
SCLK
(Input)
LRCLK
(Input)
SDIN1
SDIN2
SDIN3
T0026-01
TAS5548
SLES270 –NOVEMBER 2012 www.ti.com
7.7.2 Serial Audio Port
Serial audio port slave mode over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCLKIN
SCLK input frequency C
L
= 30 pF 2.048 12.288 MHz
t
su1
Setup time, LRCLK to SCLK rising edge 10 ns
t
h1
Hold time, LRCLK from SCLK rising edge 10 ns
t
su2
Setup time, SDIN to SCLK rising edge 10 ns
t
h2
Hold time, SDIN from SCLK rising edge 10 ns
LRCLK frequency 32 48 192 kHz
SCLK
SCLK rising edges between LRCLK rising edges 64 64
edges
SDOUT delay with respect to SCLK output (load =
20 ns
30pF)
Figure 7-1. Slave Mode Serial Data Interface Timing
7.7.3 I
2
C Serial Control Port Operation
Timing Characteristics for I
2
C Interface Signals over recommended operating conditions (unless otherwise noted)
STANDARD MODE FAST MODE
PARAMETER TEST CONDITIONS UNIT
MIN MAX MIN MAX
f
SCL
SCL clock frequency 0 100 0 400 kHz
Hold time (repeated) START
t
HD-STA
condition. After this period, the first 4 0.6 μs
clock pulse is generated.
t
LOW
LOW period of the SCL clock 4.7 1.3 μs
t
HIGH
HIGH period of the SCL clock 4 0.6 μs
t
SU-STA
Setup time for repeated START 4.7 0.6 μs
t
SU-DAT
Data setup time 250 200 ns
t
HD-DAT
Data hold time
(1) (2)
0 3.45 0 0.9 μs
20 + 0.1
t
r
Rise time of both SDA and SCL 1000 500
(4)
ns
C
b
(3)
(1) Note that SDA does not have the standard I
2
C specification 300-ns hold time and that SDA must be valid by the rising and falling edges
of SCL. TI recommends that a 3.3-kΩ pullup resistor be used to avoid potential timing issues.
(2) A fast-mode I
2
C-bus device can be used in a standard-mode I
2
C-bus system, but the requirement t
SU-DAT
≥250 ns must then be met.
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
r-max
+ t
SU-DAT
= 1000 + 250 = 1250 ns (according to the
standard-mode I
2
C bus specification) before the SCL line is released.
(3) C
b
= total capacitance of one bus line in pF.
(4) Rise time varies with pullup resistor.
50 Electrical Specifications Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TAS5548