Datasheet

TAS5548
www.ti.com SLES270 –NOVEMBER 2012
5 TAS5548 Controls and Status
The TAS5548 provides control and status information from both the I
2
C registers and device pins.
This section describes some of these controls and status functions. The I
2
C summary and detailed
register descriptions are contained in Section 10 and Section 11.
5.1 I
2
C Status Registers
The TAS5548 has two status registers that provide general device information. These are the general
status register 0 (0x01) and the error status register (0x02).
5.1.1 General Status Register (0x01)
• Device identification code
5.1.2 Error Status Register (0x02)
• No internal errors (the valid signal is high)
• Audio Clip indicator. Writing to the register clears the indicator.
• This error status register is normally used for system development only.
5.2 TAS5548 Pin Controls
The TAS5548 provide a number of terminal controls to manage the device operation. These controls are:
• RESET
• PDN
• BKND_ERR
• HP_SEL
• MUTE
• PSVC
• EMO1 (see System Power Contoller section)
• EMO2 (see System Power Contoller section)
5.2.1 Reset (RESET)
The TAS5548 is placed in the reset mode either by the power-up reset circuitry when power is applied, or
by setting the RESET terminal low.
RESET is an asynchronous control signal that restores the TAS5548 to the hard-mute state (Non PWM
Switching). Master volume is immediately set to full attenuation (there is no ramp down). Reset initiates
the device reset without an MCLK input. As long as the RESET terminal is held low, the device is in the
reset state. During reset, all I
2
C and serial data bus operations are ignored.
Table 5-1 shows the device output signals while RESET is active.
Table 5-1. Device Outputs During Reset
SIGNAL SIGNAL STATE
Valid Low
PWM P-outputs Low (Non PWM Switching)
PWM M-outputs Low (Non PWM Switching)
SDA Signal input (not driven)
Copyright © 2012, Texas Instruments Incorporated TAS5548 Controls and Status 35
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