Datasheet
7
Biquads
in
Series
Bass
and
Treble
Loudness
DRC
Input
Mixer
1 Other
Channel Output
Available For 7 & 8
32-Bit
Trunc
PWM
Proc
A_to_ipmix
B_to_ipmix
A
SDIN1
B
C_to_ipmix
D_to_ipmix
SDIN2
Left
Right
Channel V o l u m e
Bass and Treble
Bypass
Bass
and
Treble
Inline
Pre-
Vo l u m e
Post-
Vo l u m e
Output
Gain
Output Mixer Sums
Any Two Channels
PWM
Output
C
D
Left
Right
DRC
Bypass
DRC
Inline
E_to_ipmix
F_to_ipmix
E
SDIN3
F
G_to_ipmix
H_to_ipmix
SDIN4
Left
Right
G
H
Left
Right
B0016
Master
Volume
Max
Volume
IP Mixer 1
(I2C 0xXX )
6 X 4
Corssbar
Input Mixer
A
F
E
B
I
J
SDIN1-L (L) (1)
SDIN1-R (R)
SDIN3-L (C)
SDIN3-R (LFE)
MIC-L-IN
MIC-R-IN
IP Mixer 2
(I2C 0xXX )
6 X 4
Corssbar
Input Mixer
A
F
E
B
I
J
SDIN1-L (L)
SDIN1-R ( R)
(1 )
SDIN3-L (C)
SDIN3-R (LFE)
MIC-L-IN
MIC-R-IN
IP Mixer 7
(I2C 0xXX )
6 X 4
Corssbar
Input Mixer
A
F
E
B
I
J
SDIN1-L (L)
SDIN1-R (R)
SDIN3-L (C)
(1 )
SDIN3-R (LFE)
MIC-L-IN
MIC-R-IN
IP Mixer 8
(I2C 0xXX )
6 X 4
Corssbar
Input Mixer
A
F
E
B
I
J
SDIN1-L (L)
SDIN1-R (R)
SDIN3-L (C)
SDIN3-R (LFE)
(1 )
MIC-L-IN
MIC-R-IN
2 DAP 7
BQ
(0x82 -
0x83
2 DAP 7
BQ
(0x7B-
0x7C
Coeff=0 (lin), (I2C 0x4F )
Coeff=0 (lin),
(I2C 0x4C)
Coeff=1 (lin),
(I2C 0x50 )
Coeff=1 (lin),
(I2C 0x4D)
Coeff=0 (lin), (I2C 0x4B )
Coeff=0 (lin), (I2C 0x4E)
Coeff=0 (lin), (I2C 0x4A )
Coeff=0 (lin), (I2C 0x49 )
5 DAP 1
BQ
(0x51 -
0x55
5 DAP 2
BQ
(0x58 -
0x5C
4 DAP 8
BQ
(0x84 -
0x87
Bass
Treble 1
BQ
(0xXX-
0xXX
Bass
Treble 2
BQ
(0xXX-
0xXX
Bass
Treble 8
BQ
(0xXX-
0xXX
Volume
1
(0xXX-
0xXX
Volume
2
(0xXX-
0xXX
Loudnes
s 1
(0xXX-
0xXX
OP Mixer1
(I
2C 0xF4 )
4 × 2 Output
Mixer
Volume
7
(0xXX-
0xXX
Volume
8
(0xXX-
0xXX
Loudnes
s 2
(0xXX-
0xXX
Loudnes
s 8
(0xXX-
0xXX
DRC
1
(0xXX-
0xXX
DRC
1
(0xXX-
0xXX
DRC
2
(0xXX-
0xXX
OP Mixer2
(I
2C 0xF5 )
4 × 2 Output
Mixer
OP Mixer7
(I
2C 0xF6 )
4 × 3 Output
Mixer
OP Mixer8
(I
2C 0xF7 )
4 × 3 Output
Mixer
Master Vol
(0xXX)
Max VOL
THD Management
xE9, xEA
L to PWM1
R to PWM2
C to PWM7
Sub to PWM8
4 DAP
BQ
(0x7D-
0x80
7
TAS5548
www.ti.com
SLES270 –NOVEMBER 2012
(1) Default inputs
Figure 3-2. TAS5548 Architecture With I
2
C Registers in 192kHz Native Mode (f
S
= 176.4 kHz or f
S
= 192
kHz)
Figure 3-3. TAS5548 Detailed Channel Processing
Copyright © 2012, Texas Instruments Incorporated TAS5548 DAP Architecture 15
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