Datasheet

TAS5548
SLES270 –NOVEMBER 2012 www.ti.com
Table 11-40. ASRC Control (0xC4) (continued)
D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
0 ASRC2 is enabled
1 ASRC2 is bypassed
0 RESERVED
1 RESERVED
0 RESERVED
1 RESERVED
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 ASRC #1 Right Justified 16bit
0 0 0 1 ASRC #1 Right Justified 20bit
0 0 1 0 ASRC #1 Right Justified 24bit
0 0 1 1 ASRC #1 I2S 16bit
0 1 0 0 ASRC #1 I2S 20bit
0 1 0 1 ASRC #1 I2S 24bit
0 1 1 0 ASRC #1 Left Justified 16bit
0 1 1 1 ASRC #1 Left Justified 20bit
1 0 0 0 ASRC #1 Left Justified 24bit
0 0 0 0 ASRC #2 Right Justified 16bit
0 0 0 1 ASRC #2 Right Justified 20bit
0 0 1 0 ASRC #2 Right Justified 24bit
0 0 1 1 ASRC #2 I2S 16bit
0 1 0 0 ASRC #2 I2S 20bit
0 1 0 1 ASRC #2 I2S 24bit
0 1 1 0 ASRC #2 Left Justified 16bit
0 1 1 1 ASRC #2 Left Justified 20bit
1 0 0 0 ASRC #2 Left Justified 24bit
Bit D28: Having ASRC's act independently allows two sources, such as S/PDIF receiver and a bluetooth
module to be mixed comfortably, without issue if one of the sources fails/stops. Usage example: mixing
audio from games console with bluetooth audio input. If bluetooth connection is dropped, the audio from
console will not mute.
Bit D18: Select truncation of the data on the output of the SRC, with or without applied Dither. This is
based on user preference. TI suggests dithering before truncation.
Table 11-41. ASRC Mode Control 0xC5
D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
0 Disable MCLKO (PSVC output is available, Default)
1 Enable MCLKO (PSVC output is not available)
0 Disable SCLKO (SCLK2 input is available, Default)
1 Enable SCLKO (SCLK2 input is not available)
0 Disable LRCLKO (LRCLK2 input is available, Default)
1 Enable LRCLKO (LRCLK2 input is not available)
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
0 Serial clock output sampling rate is 44.1/48 kHz
1 Serial clock output sampling rate is the internal sampling rate
0 Disable SDIN5 (SDOUT is available)
100 Serial-Control Interface Register Definitions Copyright © 2012, Texas Instruments Incorporated
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