Datasheet
TAS5508C
SLES257–SEPTEMBER 2010
www.ti.com
7.24 DRC2 Data Registers (0x9D–0xA1)
DRC2 applies to channel 8.
Table 7-25. DRC2 Data Register Format
TOTAL
I
2
C
REGISTER NAME DESCRIPTION OF CONTENTS DEFAULT STATE
BYTES
SUBADDRESS
Channel 8 DRC2 energy u[31:28], E[27:24], E[23:16], E[15:8], E[7:0] 0x00, 0x00, 0x88, 0x3F
0x9D 8
Channel 8 DRC2 (1 – energy) u[31:28], 1–E[27:24], 1–E[23:16], 1–E[15:8], 1–E[7:0] 0x00, 0x7F, 0x77, 0xC0
Channel 8 DRC2 threshold u[31:24], u[23:16], T1[15:8], T1[7:0] 0x00, 0x00, 0x00, 0x00
upper 16 bits (T1)
Channel 8 DRC2 threshold T1[31:24], T1[23:16], T1[15:8], T1[7:0] 0x0B, 0x20, 0xE2, 0xB2
lower 32 bits (T1)
0x9E 16
Channel 8 DRC2 threshold u[31:24], u[23:16], T2[15:8], T2[7:0] 0x00, 0x00, 0x00, 0x00
upper 16 bits (T2)
Channel 8 DRC2 threshold T2[31:24], T2[23:16], T2[15:8], T2[7:0] 0x06, 0xF9, 0xDE, 0x58
lower 32 bits (T2)
Channel 8 DRC2 slope (k0) u[31:28], k0[27:24], k0[23:16], k0[15:8], k0[7:0] 0x00, 0x40, 0x00, 0x00
0x9F 12 Channel 8 DRC2 slope (k1) u[31:28], k1[27:24], k1[23:16], k1[15:8], k1[7:0] 0x0F, 0xC0, 0x00, 0x00
Channel 8 DRC2 slope (k2) u[31:28], k2[27:24], k2[23:16], k2[15:8], k2[7:0] 0x0F, 0x90, 0x00, 0x00
Channel 8 DRC2 offset 1 upper u[31:24], u[23:16], O1[15:8], O1[7:0] 0x00, 0x00, 0xFF, 0xFF
16 bits (O1)
Channel 8 DRC2 offset 1 lower O1[31:24], O1[23:16], O1[15:8], O1[7:0] 0xFF, 0x82, 0x30, 0x98
32 bits (O1)
0xA0 16
Channel 8 DRC2 offset 2 upper u[31:24], u[23:16], O2[15:8], O2[7:0] 0x00, 0x00, 0x00, 0x00
16 bits (O2)
Channel 8 DRC2 offset 2 lower O2[31:24], O2[23:16], O2[15:8], O2[7:0] 0x01, 0x95, 0xB2, 0xC0
32 bits (O2)
Channel 8 DRC2 attack u[31:28], A[27:24], A[23:16], A[15:8], A[7:0] 0x00, 0x00, 0x88, 0x3F
Channel 8 DRC2 (1 – attack) u[31:28], 1–A[27:24], 1–A[23:16], 1–A[15:8], 1–A[7:0] 0x00, 0x7F, 0x77, 0xC0
0xA1 16
Channel 8 DRC2 decay u[31:28], D[27:24], D[23:16], D[15:8], D[7:0] 0x00, 0x00, 0x00, 0x56
Channel 8 DRC2 (1 – decay) u[31:28], 1–D[27:24], 1–D[23:16], 1–D[15:8], 1–D[7:0] 0x00, 0x3F, 0xFF, 0xA8
7.25 DRC Bypass Registers (0xA2–0xA9)
DRC bypass/inline for channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0xA2, 0xA3, 0xA4,
0xA5, 0xA6, 0xA7, 0xA8, and 0xA9, respectively. Eight bytes are written for each channel. Each gain
coefficient is in 28-bit (5.23) format, so 0x0080 0000 is a gain of 1. Each gain coefficient is written as a
32-bit word with the upper 4 bits not used.
To enable DRC for a given channel (with unity gain), bypass = 0x0000 0000 and inline = 0x0080 0000.
To disable DRC for a given channel, bypass = 0x0080 0000 and inline = 0x0000 0000.
Table 7-26. DRC Bypass Register Format
TOTAL
REGISTER NAME CONTENTS INITIALIZATION VALUE
BYTES
Channel bass DRC bypass u[31:28], bypass[27:24], bypass[23:16], bypass[15:8], bypass[7:0] 0x00, 0x80, 0x00, 0x00
8
Channel DRC inline u[31:28], inline[27:24], inline[23:16], inline[15:8], inline[7:0] 0x00, 0x00, 0x00, 0x00
7.26 8×2 Output Mixer Registers (0xAA–0xAF)
Output mixers for channels 1–6 map to registers 0xAA–0xAF.
Total data per register is 8 bytes.
88 Serial-Control Interface Register Definitions Copyright © 2010, Texas Instruments Incorporated
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