Datasheet

TAS5508C
SLES257–SEPTEMBER 2010 www.ti.com
7.3 Error Status Register (0x02)
Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software
must clear the register (write zeroes) and then read them to determine if there are any persistent errors.
Table 7-3. Error Status Register Format
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
1 – – – – – – – PLL phase lock error
– 1 – – – – – – PLL auto lock error
– – 1 – – – – – SCLK error
– – – 1 – – – – LRCLK error
– – – – 1 – – – Frame slip
0 0 0 0 0 0 0 0 No errors
7.4 System Control Register 1 (0x03)
Bits D5, D2, D1, and D0 are Don't Care.
Table 7-4. System Control Register 1 Format
D7 D6 D5 D4 D3 D2 D1 D0 Function
0 – – – PWM high pass disabled
1 – – – PWM high pass enabled
– – 0 Soft unmute on recovery from clock error
– – 1 Hard unmute on recovery from clock error
– – – 1 PSVC Hi-Z enable
– – – 0 PSVC Hi-Z disable
7.5 System Control Register 2 (0x04)
Bits D3 and D2 are Don't Care.
Table 7-5. System Control Register 2 Format
D7 D6 D5 D4 D3 D2 D1 D0 Function
0 – – – – – Reserved
– 0 – – – – PWM automute detection enabled
– 1 – – – – PWM automute detection disabled
0 – – – 8-Ch device input detection automute enabled
– – 1 – – – 8-Ch device input detection automute disabled
– – – 0 – – Unmute threshold 6 dB over input threshold
– – – 1 – – Unmute threshold equal to input threshold
– – – – 0 0 No de-emphasis
– – – – 0 1 De-emphasis for Fs = 32 kHz
– – – – 1 0 De-emphasis for Fs = 44.1 kHz
– – – – 1 1 De-emphasis for Fs = 48 kHz
7.6 Channel Configuration Control Registers (0x05–0x0C)
Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, and 0x0C,
respectively.
Bit D0 is Don't Care.
74 Serial-Control Interface Register Definitions Copyright © 2010, Texas Instruments Incorporated
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