Datasheet

TAS5508C
www.ti.com SLES257–SEPTEMBER 2010
7 Serial-Control Interface Register Definitions
Unless otherwise noted, the I
2
C register default values are in bold font.
Note that u indicates unused bits.
7.1 Clock Control Register (0x00)
Bit D1 is Don't Care.
Table 7-1. Clock Control Register Format
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 – – – – 32-kHz data rate
0 0 1 – – – – 38-kHz data rate
0 1 0 – – – – 44.1-kHz data rate
0 1 1 – – – – 48-kHz data rate
1 0 0 – – – – 88.2-kHz data rate
1 0 1 – – – – 96-kHz data rate
1 1 0 – – – – 176.4-kHz data rate
1 1 1 – – – – 192-kHz data rate
– – – 0 0 0 MCLK frequency = 64
– – – 0 0 1 MCLK frequency = 128
– – – 0 1 0 MCLK frequency = 192
– – – 0 1 1 MCLK frequency = 256
– – – 1 0 0 MCLK frequency = 384
– – – 1 0 1 MCLK frequency = 512
– – – 1 1 0 MCLK frequency = 768
– – – 1 1 1 Reserved
– – – – – – 1 Clock register is valid (read-only)
– – – – – – 0 Clock register is not valid (read-only)
7.2 General Status Register 0 (0x01)
Table 7-2. General Status Register Format
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
1 – – – – – – – Clip indicator
– 1 – – – – – – Bank switching busy
– – 0 0 0 0 0 1 Identification code for TAS5508C
Copyright © 2010, Texas Instruments Incorporated Serial-Control Interface Register Definitions 73
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