Datasheet

TAS5508C
www.ti.com SLES257–SEPTEMBER 2010
List of Tables
2-1 Serial Data Formats.............................................................................................................. 19
2-2 TAS5508C Audio Processing Feature Sets .................................................................................. 21
2-3 Contents of One 20-Byte Biquad Filter Register (Default = All-Pass)..................................................... 29
2-4 Bass and Treble Filter Selections .............................................................................................. 30
2-5 Linear Gain Step Size ........................................................................................................... 30
2-6 Default Loudness Compensation Parameters................................................................................ 32
2-7 Loudness Function Parameters ................................................................................................ 33
2-8 DRC Recommended Changes From TAS5508C Defaults ................................................................. 34
3-1 Device Outputs During Reset................................................................................................... 43
3-2 Values Set During Reset ........................................................................................................ 44
3-3 Device Outputs During Power Down .......................................................................................... 45
3-4 Device Outputs During Back-End Error ....................................................................................... 46
3-5 Description of the Channel Configuration Registers (0x05 to 0x0C) ...................................................... 47
3-6 Recommended TAS5508C Configurations for Texas Instruments Power Stages....................................... 48
3-7 Audio System Configuration (General Control Register 0xE0)............................................................. 49
3-8 Volume Ramp Rates in ms ..................................................................................................... 50
3-9 Interchannel Delay Default Values............................................................................................. 50
7-1 Clock Control Register Format ................................................................................................. 73
7-2 General Status Register Format................................................................................................ 73
7-3 Error Status Register Format ................................................................................................... 74
7-4 System Control Register 1 Format............................................................................................. 74
7-5 System Control Register 2 Format............................................................................................. 74
7-6 Channel Configuration Control Register Format ............................................................................. 75
7-7 Headphone Configuration Control Register Format ......................................................................... 75
7-8 Serial Data Interface Control Register Format ............................................................................... 75
7-9 Soft Mute Register Format ...................................................................................................... 76
7-10 Automute Control Register Format............................................................................................. 77
7-11 Automute PWM Threshold and Back-End Reset Period Register Format................................................ 78
7-12 Modulation Index Limit Register Format ...................................................................................... 79
7-13 Interchannel Delay Register Format ........................................................................................... 79
7-14 Channel Offset Register Format................................................................................................ 79
7-15 Bank-Switching Command Register Format.................................................................................. 80
7-16 Channel 1–8 Input Mixer Register Format .................................................................................... 81
7-17 Bass Management Register Format ........................................................................................... 84
7-18 Biquad Filter Register Format .................................................................................................. 84
7-19 Contents of One 20-Byte Biquad Filter Register (Default = All-Pass)..................................................... 85
7-20 Channel 1–8 Bass and Treble Bypass Register Format .................................................................... 85
7-21 Loudness Register Format...................................................................................................... 85
7-22 Channel 1–7 DCR1 Control Register Format................................................................................. 86
7-23 Channel-8 DRC2 Control Register Format ................................................................................... 87
7-24 DRC1 Data Register Format.................................................................................................... 87
7-25 DRC2 Data Register Format.................................................................................................... 88
7-26 DRC Bypass Register Format .................................................................................................. 88
7-27 Output Mixer Register Format (Upper 4 Bytes) .............................................................................. 89
7-28 Output Mixer Register Format (Lower 4 Bytes) .............................................................................. 89
7-29 Output Mixer Register Format (Upper 4 Bytes) .............................................................................. 90
7-30 Output Mixer Register Format (Middle 4 Bytes).............................................................................. 90
Copyright © 2010, Texas Instruments Incorporated List of Tables 7