Datasheet

TAS5508C
www.ti.com SLES257–SEPTEMBER 2010
6 Serial-Control I
2
C Register Summary
The TAS5508C slave address is 0x36. See Serial-Control Interface Register Definitions, Section 7 for
complete bit definitions.
Note that u indicates unused bits.
TOTAL
I
2
C
REGISTER FIELDS DESCRIPTION OF CONTENTS DEFAULT STATE
BYTES
SUBADDRESS
0x00 1 Clock control register Set data rate and MCLK frequency 1. Fs = 48 kHz
2. MCLK = 256 Fs = 12.288 MHz
0x01 1 General status register Clip indicator and ID code for the 0x01
TAS5508C
0x02 1 Error status register PLL, SCLK, LRCLK, and frame slip No errors
errors
1. PWM high pass disabled
PWM high pass, clock set, unmute 2. Auto clock set
0x03 1 System control register 1
select, PSVC select 3. Hard unmute on clock error recovery
4. PSVC Hi-Z disabled
1. Automute time-out disabled
2. Post-DAP detection automute enabled
0x04 1 System control register 2 Automute and de-emphasis control 3. 8-Ch device input detection automute enabled
4. Unmute threshold 6 dB over input
5. No de-emphasis
1. Enable back-end reset.
2. Valid low for reset
3. Valid low for mute
Channel configuration Configure channels 1, 2, 3, 4, 5, 6, 7,
0x05–0x0C 1/reg. 4. Normal BEPolarity
control registers and 8
5. Do not remap the output for the TAS5182.
6. Do not go low-low in mute.
7. Do not remap Hi-Z state to low-low state.
1. Disable back-end reset sequence.
2. Valid does not have to be low for reset.
3. Valid does not have to be low for mute.
Headphone configuration
0x0D 1 Configure headphone output 4. Normal BEPolarity
control register
5. Do not remap output to comply with 5182.
6. Do not go low-low in mute.
7. Do not remap Hi-Z state to low-low state.
0x0E 1 Serial data interface control Set serial data interface to
24-bit I
2
S
register
right-justified, I
2
S, or left-justified.
0x0F 1 Soft mute register Soft mute for channels 1, 2, 3, 4, 5, 6, Unmute all channels.
7, and 8
0x10–0x13 Reserved
0x14 1 Automute control register Set automute delay and threshold. 1. Set automute delay = 5 ms.
2. Set automute threshold less than bit 8.
0x15 1 Automute PWM threshold Set PWM automute threshold; set 1. Set the PWM threshold the same as the
and back-end reset period back-end reset period. TAS5508C input threshold.
register 2. Set back-end reset period = 5 ms.
0x16 1 Modulation index limit Set modulation index. 97.7%
register
0x17–0x1A Reserved
Channel 1 delay = –23 DCLK periods
Channel 2 delay = 0 DCLK periods
Channel 3 delay = –16 DCLK periods
Channel 4 delay = 16 DCLK periods
0x1B–0x22 1/reg. Interchannel delay registers Set interchannel delay.
Channel 5 delay = –24 DCLK periods
Channel 6 delay = 8 DCLK periods
Channel 7 delay = –8 DCLK periods
Channel 8 delay = 24 DCLK periods
0x23 1 Channel offset register Absolute delay offset for channel 1 Minimum absolute default = 0 DCLK periods
(0–255)
0x24–0x3F Reserved
0x40 4 Bank-switching command Set up DAP coefficients bank Manual selection – bank 1
register switching for banks 1, 2, and 3
Copyright © 2010, Texas Instruments Incorporated 69
Serial-Control I
2
C Register Summary
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