Datasheet

A6 A5 A4 A3 A2 A1 A0
R/W
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I CDevice Addressand
Read/WriteBit
2
Subaddress DataByte
T0481-01
D7 D0 ACK
Stop
Condition
Acknowledge
I CDevice Addressand
Read/WriteBit
2
Subaddress LastDataByte
A6 A5 A1 A0 R/W ACK A7 A5 A1 A0 ACK D7 ACK
Start
Condition
Acknowledge Acknowledge Acknowledge
FirstDataByte
A4 A3A6
OtherDataBytes
ACK
Acknowledge
D0 D7 D0
T0482-01
TAS5508C
SLES257–SEPTEMBER 2010 www.ti.com
During multiple-byte write operations, the TAS5508C compares the number of bytes transmitted to the
number of bytes that are required for each specific subaddress. If a write command is received for a
biquad subaddress, the TAS5508C expects to receive five 32-bit words. If fewer than five 32-bit data
words have been received when a stop command (or another start command) is received, the data
received is discarded. Similarly, if a write command is received for a mixer coefficient, the TAS5508C
expects to receive one 32-bit word.
Supplying a subaddress for each subaddress transaction is referred to as random I
2
C addressing. The
TAS5508C also supports sequential I
2
C addressing. For write transactions, if a subaddress is issued
followed by data for that subaddress and the 15 subaddresses that follow, a sequential I
2
C write
transaction has taken place, and the data for all 16 subaddresses is successfully received by the
TAS5508C. For I
2
C sequential write transactions, the subaddress then serves as the start address and the
amount of data subsequently transmitted, before a stop or start is transmitted, determines how many
subaddresses are written. As is true for random addressing, sequential addressing requires that a
complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data
for the last subaddress is discarded. However, all other data written is accepted; only the incomplete data
is discarded.
5.3 Single-Byte Write
As shown in Figure 5-2, a single-byte, data-write transfer begins with the master device transmitting a start
condition followed by the I
2
C device address and the read/write bit. The read/write bit determines the
direction of the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct
I
2
C device address and the read/write bit, the TAS5508C device responds with an acknowledge bit. Next,
the master transmits the address byte or bytes corresponding to the TAS5508C internal memory address
being accessed. After receiving the address byte, the TAS5508C again responds with an acknowledge bit.
Next, the master device transmits the data byte to be written to the memory address being accessed. After
receiving the data byte, the TAS5508C again responds with an acknowledge bit. Finally, the master
device transmits a stop condition to complete the single-byte, data-write transfer.
Figure 5-2. Single-Byte Write Transfer
5.4 Multiple-Byte Write
A multiple-byte, data-write transfer is identical to a single-byte, data-write transfer except that multiple data
bytes are transmitted by the master device to TAS5508C, as shown in Figure 5-3. After receiving each
data byte, the TAS5508C responds with an acknowledge bit.
Figure 5-3. Multiple-Byte Write Transfer
66 Copyright © 2010, Texas Instruments Incorporated
I
2
C Serial-Control Interface (Slave Address 0x36)
Submit Documentation Feedback
Product Folder Link(s): TAS5508C