Datasheet

23
22
SCLK
32Clks
LRCLK(NoteReversedPhase)
LeftChannel
24-BitMode
1
19 18
20-BitMode
16-BitMode
15
14
MSB LSB
32Clks
RightChannel
2-ChannelI S(PhilipsFormat)StereoInput
2
T0034-01
5
4
9 8
1
0
0
4
5
1
0
23
22 1
19 18
15
14
MSB LSB
5
4
9 8
1
0
0
4
5
1
0
SCLK
TAS5508C
SLES257–SEPTEMBER 2010 www.ti.com
4.7.9 Volume Control
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Individual volume, master volume, or a
Maximum attenuation before mute –127 dB
combination of both
Maximum gain Individual volume, master volume 18 dB
Maximum volume before the onset of clipping 0-dB input, any modulation limit 0 dB
PSVC range PSVC enabled 12, 18, or 24 dB
PSVC rate Fs
PSVC modulation Single sided
PSVC quantization 2048 Steps
6% 95%
PSVC PWM modulation limits PSVC range = 24 dB dB
(120 : 2048) (1944 : 2048)
4.8 Serial Audio Interface Control and Timing
4.8.1 I
2
S Timing
I
2
S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 64 × Fs is
used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the
first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS5508C masks unused trailing data bit positions.
Figure 4-9. I
2
S 64-Fs Format
62 Electrical Specifications Copyright © 2010, Texas Instruments Incorporated
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