Datasheet

t
h1
t
su1
t
su2
t
h2
SCLK
(Input)
LRCLK
(Input)
SDIN1
SDIN2
SDIN3
T0026-01
TAS5508C
www.ti.com SLES257–SEPTEMBER 2010
4.7.2 Serial Audio Port
Serial audio port slave mode over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCLKIN
SCLK input frequency C
L
= 30 pF,SCLK = 64 × Fs 2.048 12.288 MHz
t
su1
Setup time, LRCLK to SCLK rising edge 10 ns
t
h1
Hold time, LRCLK from SCLK rising edge 10 ns
t
su2
Setup time, SDIN to SCLK rising edge 10 ns
t
h2
Hold time, SDIN from SCLK rising edge 10 ns
LRCLK frequency 32 48 192 kHz
SCLK duty cycle 40% 50% 60%
LRCLK duty cycle 40% 50% 60%
SCLK
SCLK rising edges between LRCLK rising edges 64 64
edges
LRCLK clock edge with respect to the falling edge of SCLK
–1/4 1/4
SCLK period
Figure 4-1. Slave Mode Serial Data Interface Timing
Copyright © 2010, Texas Instruments Incorporated Electrical Specifications 57
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