Datasheet

TAS5508C
www.ti.com SLES257–SEPTEMBER 2010
The master mute terminal is used to support a variety of other operations in the TAS5508C, such as
setting the interchannel delay, the biquad coefficients, the serial interface format, and the clock rates. A
mute command by the master mute terminal, individual I
2
C mute, the AM interference mute sequence, the
bank switch mute sequence, or automute overrides an unmute command or a volume command. While a
mute is active, the commanded channels are placed in a mute state. When a channel is unmuted, it goes
to the last commanded volume setting that has been received for that channel.
3.3 Device Configuration Controls
The TAS5508C provides a number of system configuration controls that are set at initialization and
following a reset.
• Channel configuration
• Headphone configuration
• Audio system configurations
• Recovery from clock error
• Power-supply volume-control enable
• Volume and mute update rate
• Modulation index limit
• Interchannel delay
• Master clock and data rate controls
• Bank controls
3.3.1 Channel Configuration Registers
For the TAS5508C to have full control of the power stages, registers 0x05 to 0x0C must be programmed
to reflect the proper power stage and how each one should be controlled. There are eight channel
configuration registers, one for each channel.
The primary reason for using these registers is that different power stages require different handling
during start-up, mute/unmute, shutdown, and error recovery. The TAS5508C must select the sequence
that gives the best click and pop performance and ensures that the bootstrap capacitor is charged
correctly during start-up. This sequence depends on which power stage is present at the TAS5508C
output.
Table 3-5. Description of the Channel Configuration Registers (0x05 to 0x0C)
BIT DESCRIPTION
D7 Enable/disable error recovery sequence. In case the BKND_RECOVERY pin is pulled low, this register determines if this
channel is to follow the error recovery sequence or to continue with no interruption.
D6 Determines if the power stage needs the TAS5508C VALID pin to go low to reset the power stage. Some power stages can be
reset by a combination of PWM signals. For these devices, it is recommended to set this bit low, because the VALID pin is
shared for power stages. This provides better control of each power stage.
D5 Determines if the power stage needs the TAS5508C VALID pin to go low to mute the power stage. Some power stages can be
muted by a combination of PWM signals. For these devices, it is recommended to set this bit low, because the VALID pin is
shared for power stages. This provides better control of each power stage.
D4 Inverts the PWM output. Inverting the PWM output can be an advantage if the power stage input pin is opposite the TAS5508C
PWM pinout. This makes routing on the PCB easier. To keep the phase of the output, the speaker terminals must also be
inverted.
D3 The power stage TAS5182 has a special PWM input. To ensure that the TAS5508C has full control in all occasions, the PWM
output must be remapped.
D2 Can be used to handle click and pop for some applications.
D1 This bit is normally used together with D2. For some power stages, both PWM signals must be high to get the desired operation
of both speaker outputs to be low. This bit sets the PWM outputs high-high during mute.
D0 Not used
Copyright © 2010, Texas Instruments Incorporated TAS5508C Controls and Status 47
Submit Documentation Feedback
Product Folder Link(s): TAS5508C