Datasheet

TAS5508C
www.ti.com SLES257–SEPTEMBER 2010
Table 2-1. Serial Data Formats
RECEIVE SERIAL DATA FORMAT WORD LENGTH
Right-justified 16
Right-justified 20
Right-justified 24
I
2
S 16
I
2
S 20
I
2
S 24
Left-justified 16
Left-justified 20
Left-justified 24
Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5508C accepts 16-, 20-, or 24-bit
serial data at 32, 38, 44.1, 48, 88.2, 96, 176.4, or 192 kHz in left-justified, I
2
S, or right-justified format.
Data is input using a 64-Fs SCLK clock and an MCLK rate of 128, 192, 256, 384, 512, or 768 Fs, up to a
maximum of 50 MHz. The clock speed and serial data format are I
2
C configurable.
2.2.3 I
2
C Serial-Control Interface
The TAS5508C has an I
2
C serial-control slave interface (address 0x36) to receive commands from a
system controller. The serial-control interface supports both normal-speed (100 kHz) and high-speed (400
kHz) operations without wait states. Because the TAS5508C has a crystal time base, this interface
operates even when MCLK is absent.
The serial control interface supports both single-byte and multiple-byte read/write operations for status
registers and the general control registers associated with the PWM. However, for the DAP
data-processing registers, the serial control interface also supports multiple-byte (4-byte) write operations.
The I
2
C supports a special mode which permits I
2
C write operations to be broken up into multiple
data-write operations that are multiples of 4 data bytes. These are 6-byte, 10-byte, 14-byte, 18-byte, etc.,
write operations that are composed of a device address, read/write bit, subaddress, and any multiple of 4
bytes of data. This permits the system to incrementally write large register values without blocking other
I
2
C transactions. In order to use this feature, the first block of data is written to the target I
2
C address, and
each subsequent block of data is written to a special append register (0xFE) until all the data is written
and a stop bit is sent. An incremental read operation is not supported.
2.2.4 Device Control
The TAS5508C control section provides the control and sequencing for the TAS5508C. The device control
provides both high- and low-level control for the serial control interface, clock and serial data interfaces,
digital audio processor, and pulse-width modulator sections.
2.2.5 Digital Audio Processor (DAP)
The DAP arithmetic unit is used to implement all audio-processing functions: soft volume, loudness
compensation, bass and treble processing, dynamic range control, channel filtering, input and output
mixing. Figure 2-3 shows the TAS5508C DAP architecture.
The DAP accepts 24-bit data from the serial data interface and outputs 32-bit data to the PWM section.
The DAP supports two configurations, one for 32-kHz to 96-kHz data and one for 176.4-kHz to 192-kHz
data.
2.2.5.1 TAS5508C Audio-Processing Configurations
The 32-kHz to 96-kHz configuration supports eight channels of data processing that can be configured
either as eight channels, or as six channels with two channels for separate stereo line outputs.
Copyright © 2010, Texas Instruments Incorporated Description 19
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