Datasheet

TAS5508C

SLES257–SEPTEMBER 2010

www.ti.com

• Clock, PLL, and serial data interface

• I

C serial-control interface

• Device control

• Digital audio processor (DAP)

2.2.1 Power Supply

The power-supply section contains supply regulators that provide analog and digital regulated power for

various sections of the TAS5508C. The analog supply supports the analog PLL, whereas digital supplies

support the digital PLL, the digital audio processor (DAP), the pulse-width modulator (PWM), and the

output control (reclocker). The regulators can also be turned off when terminals RESET and PDN are both

low.

2.2.2 Clock, PLL, and Serial Data Interface

The TAS5508C is a clocked slave-only device that requires the use of an external 13.5-MHz crystal. It

accepts MCLK, SCLK, and LRCLK as inputs only.

The TAS5508C uses the external crystal to provide a time base for:

• Continuous data and clock error detection and management

• Automatic data-rate detection and configuration

• Automatic MCLK-rate detection and configuration (automatic bank switching)

• Supporting I

C operation/communication while MCLK is absent

The TAS5508C automatically handles clock errors, data-rate changes, and master-clock frequency

changes without requiring intervention from an external system controller. This feature significantly

reduces system complexity and design.

2.2.2.1 Serial Audio Interface

The TAS5508C operates as a slave-only/receive-only serial data interface in all modes. The TAS5508C

has four PCM serial data interfaces to permit eight channels of digital data to be received though the

SDIN1, SDIN2, SDIN3, and SDIN4 inputs. The serial audio data is in MSB-first, 2s-complement format.

The serial data input interface of the TAS5508C can be configured in right-justified, I

S, or left-justified

modes. The serial data interface format is specified using the I

C data-interface control register. The

supported formats and word lengths are shown in Table 2-1.

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