TAS5508C 8-Channel Digital Audio PWM Processor Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com Contents 1 2 3 2 ............................................................................................................... 9 1.1 Features ...................................................................................................................... 9 1.2 Overview .................................................................................................................... 10 1.3 TAS5508C System Diagrams ..................................
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 3.2 3.1.2 Error Status Register (0x02) .................................................................................. 43 TAS5508C Pin Controls .................................................................................................. 43 ................................................................................................. 43 3.2.2 Power Down (PDN) ..........................................................................................
TAS5508C SLES257 – SEPTEMBER 2010 .......................................................................................... 64 .................................................................. 65 5.1 General I2C Operation .................................................................................................... 65 5.2 Single- and Multiple-Byte Transfers ..................................................................................... 65 5.3 Single-Byte Write ................................
TAS5508C www.ti.com 8 SLES257 – SEPTEMBER 2010 ........................................................................................... 99 ........................................................................................ 99 7.38 Incremental Multiple-Write Append Register (0xFE) .................................................................. 99 TAS5508C Example Application Schematic ......................................................................... 101 7.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com List of Figures 1-1 TAS5508C Functional Structure................................................................................................ 12 1-2 Typical TAS5508C Application (DVD Receiver) 1-3 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 5-1 5-2 5-3 5-4 5-5 6 .............................................................................
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 List of Tables 2-1 Serial Data Formats .............................................................................................................. 19 2-2 TAS5508C Audio Processing Feature Sets 2-3 2-4 2-5 2-6 2-7 2-8 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 ...............................................................
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com 7-31 Output Mixer Register Format (Lower 4 Bytes) .............................................................................. 90 7-32 Volume Biquad Register Format (Default = All-Pass) ....................................................................... 91 7-33 Volume Gain Update Rate (Slew Rate) ....................................................................................... 92 7-34 Treble and Bass Gain Step Size (Slew Rate) ...............
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 8-Channel Digital Audio PWM Processor Check for Samples: TAS5508C 1 Introduction PWM 1.1 Features 1234 • General Features – Automated Operation With an Easy-to-Use Control Interface – I2C Serial-Control Slave Interface – Integrated AM Interference-Avoidance Circuitry – Single, 3.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com Operation – Intelligent AM Interference-Avoidance System Provides Clear AM Reception – Power-Supply Volume Control (PSVC) 1.2 Support for Enhanced Dynamic Range in High-Performance Applications – Adjustable Modulation Limit Overview The TAS5508C is an 8-channel digital pulse-width modulator (PWM) that provides both advanced performance and a high level of system integration.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS5508C MUTE HP_SEL BKND_ERR RESET PDN SCL I2 C Serial Control I/F Clock, PLL, and Serial Data I/F SDA SDIN1 SDIN2 SDIN3 SDIN4 PLL_FLTM PLL_FLTP OSC CAP SCLK LRCLK MCLK XTL_OUT XTL_IN AVSS AVDD DVSS DVDD VRD_PLL VRA_PLL VBGAP AVDD_REF AVSS_PLL AVDD_PLL VR_PLL Device Control Power Supply 8 × 8 Crossbar Mixer 8 9 DAP Control 4 Volume Control 8 8 2 2 8 8 DC De Interpolate SRC NS PWM Blo
TAS5508C SLES257 – SEPTEMBER 2010 1.3 www.ti.com TAS5508C System Diagrams Typical applications for the TAS5508C are 6- to 8-channel audio systems such as DVD or AV receivers. Figure 1-2 shows the basic system diagram of the DVD receiver. Power Supply AM FM T uner T exas Instruments Digital Audio Amplifier T AS5508C DVD Loader MPEG Decoder Front-Panel Controls Figure 1-2.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 TAS5508C Figure 1-3.
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TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 2 Description 2.1 Physical Characteristics 2.1.
TAS5508C SLES257 – SEPTEMBER 2010 2.1.3 www.ti.com PIN Descriptions PIN NAME NO. AVDD_PLL TYPE (1) 5-V TOLERANT TERMINATION (2) DESCRIPTION 9 P 3.3-V analog power supply for PLL. This terminal can be connected to the same power source used to drive power terminal DVDD, but to achieve low PLL jitter, this terminal should be bypassed to AVSS_PLL with a 0.1-mF low-ESR capacitor. 5, 6 P Analog ground AVSS_PLL 8 P Analog ground for PLL.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 PIN NAME NO.
TAS5508C SLES257 – SEPTEMBER 2010 • • • • 2.2.1 www.ti.com Clock, PLL, and serial data interface I2C serial-control interface Device control Digital audio processor (DAP) Power Supply The power-supply section contains supply regulators that provide analog and digital regulated power for various sections of the TAS5508C.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 Table 2-1. Serial Data Formats RECEIVE SERIAL DATA FORMAT WORD LENGTH Right-justified 16 Right-justified 20 Right-justified 24 I2S 16 2 I S 20 I2S 24 Left-justified 16 Left-justified 20 Left-justified 24 Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5508C accepts 16-, 20-, or 24-bit serial data at 32, 38, 44.1, 48, 88.2, 96, 176.4, or 192 kHz in left-justified, I2S, or right-justified format.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com The 176.4-kHz to 192-kHz configuration supports three channels of signal processing with five channels passed though (or derived from the three processed channels). To support efficiently the processing requirements of both multichannel 32-kHz to 96-kHz data and the 2-channel 176.4-kHz and 192-kHz data, the TAS5508C has separate audio-processing features for 32-kHz to 96-kHz data rates and for 176.4 kHz and 192 kHz.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 Table 2-2. TAS5508C Audio Processing Feature Sets FEATURE 32 kHz–96 kHz 8-CHANNEL FEATURE SET Signal-processing channels 8 Pass-through channels Master volume 176.
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TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 2−23 Bit 2−4 Bit 2−1 Bit 20 Bit 23 Bit Sign Bit S_xxxx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx M0007-01 Figure 2-4. 5.23 Format The decimal value of a 5.23 format number can be found by following the weighting shown in Figure 2-5. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com concatenated with the hex value of the fractional part of the gain coefficient to form the 32-bit I2C coefficient. The reason is that the 28-bit coefficient contains 5 bits of integer, and thus the integer part of the coefficient occupies all of one hex digit and the most significant bit of the second hex digit.
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TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com Ideal Input Possible Outputs Desired Output Values Retained by Overflow Bits Overflow Maximum Signal Amplitude Filter Operation Signal Bits Input Reduced SNR Signal Output Signal Bits Output Noise Floor With No Additional Precision Noise Floor as a Result of Additional Precision M0010-01 Figure 2-10. TAS5508C Digital Audio Processing 2.4 Input Crossbar Mixer The TAS5508C has a full 8×8 input crossbar mixer.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 The direct form I structure provides a separate delay element and mixer (gain coefficient) for each node in the biquad filter. Each mixer output is a signed 76-bit product of a signed 48-bit data sample (25.23 format number) and a signed 28-bit coefficient (5.23 format number), as shown in Figure 2-12. The 76-bit ALU in the TAS5508C allows the 76-bit resolution to be retained when summing the mixer outputs (filter products).
TAS5508C SLES257 – SEPTEMBER 2010 • • www.ti.com L and R Sub The bass and treble filters use a soft update rate that does not produce artifacts during adjustment. Table 2-4. Bass and Treble Filter Selections 3-dB CORNER FREQUENCIES FS (kHz) FILTER SET 1 FILTER SET 2 FILTER SET 3 FILTER SET 4 FILTER SET 5 BASS TREBLE BASS TREBLE BASS TREBLE BASS TREBLE BASS TREBLE 32 42 917 83 1833 125 3000 146 3667 167 4333 38 49 1088 99 2177 148 3562 173 4354 198 5146 44.
TAS5508C www.ti.com • SLES257 – SEPTEMBER 2010 Output automute: A single channel is muted when the output of the DAP section is less in magnitude than the input threshold value for a programmable amount of time. The detection period and thresholds for these two detectors are the same. This time interval is selectable via I2C to be from 1 ms to 110 ms. The increments of time are 1, 2, 3, 4, 5, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, and 110 ms. This interval is independent of the sample rate.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com The TAS5508C has a single set of loudness controls for the eight channels. In 6-channel mode, loudness is available to the six speaker outputs and also to the line outputs. The loudness control input uses the maximum individual master volume (V) to control the loudness that is applied to all channels. In the 192-kHz and 176.4-kHz modes, the loudness function is active only for channels 1, 2, and 8.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 Table 2-7. Loudness Function Parameters DATA FORMAT I2C SUBADDRESS Controls shape of Loudness curves 5.23 Loudness gain Loudness function LO Loudness offset G Gain O Offset LOUDNESS TERM DESCRIPTION H(Z) Loudness biquad LG USAGE DEFAULT HEX FLOAT 0x95 b0 = 0000 8ACE b1 = 0000 0000 b2 = FFFF 7532 a1 = FF01 1951 a2 = 007E E914 b0 = 0.004236 b1 = 0 b2 = –0.004236 a1 = –1.991415 a2 = 0.991488 5.23 0x91 FFC0 0000 –0.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com All of the TAS5508C default values for DRC can be used except for the DRC1 decay and DRC2 decay. Table 2-8 shows the recommended time constants and their hex values. If the user wants to implement other DRC functions, Texas Instruments recommends using the automatic loudspeaker equalization (ALE) tool available from Texas Instruments. The ALE tool allows the user to select the DRC transfer function graphically.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 DRC − Compensated Output Region 0 Region 1 Region 2 k2 k1 1:1 Transfer Function Implemented Transfer Function k0 O2 O1 T1 T2 DRC Input Level M0014-01 Figure 2-17. Dynamic Range Compression (DRC) Transfer Function Structure The three regions shown in Figure 2-17 are defined by three sets of programmable coefficients: • Thresholds T1 and T2 define region boundaries.
TAS5508C SLES257 – SEPTEMBER 2010 • • www.ti.com Offsets O1 and O2 define, in dB, the attenuation (cut) or gain (boost) applied by the DRC-derived gain coefficient at the threshold points T1 and T2, respectively. Positive offsets are defined as cuts, and thus boost or gain selections are negative numbers. Offsets must be programmed as 48-bit (25.23 format) numbers.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 Threshold T2 serves as the fulcrum or pivot point in the DRC transfer function. O2 defines the boost (> 0 dB) or cut (< 0 dB) implemented by the DRC-derived gain coefficient for an rms input level of T2. If O2 = 0 dB, the value of the derived gain coefficient is 1 (0x0080 0000 in 5.23 format). k2 is the slope of the DRC transfer function for rms input levels above T2, and k1 is the slope of the DRC transfer function for rms input levels below T2 (and above T1).
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com O1 INPUT + –21 dB ) 24.0824 dB + 0.51197555 6.0206 + 0.1000_0011_0001_1101_0100 + 0x00000041886A in 25.23 format 2.10.2.3 Slope Parameter Computation In developing the equations used to determine the subaddress of the input value required to realize a given compression or expansion within a given region of the DRC, the following convention is adopted.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 Gain Coefficient 28 Select Output N 48 Gain Coefficient 48 28 Select Output N 48 48 Output 1, 2, 3, 4, 5, or 6 Output 7 or 8 Gain Coefficient 28 Select Output N 48 Gain Coefficient 48 28 Select Output N 48 48 Gain Coefficient 48 28 Select Output N 48 M0011-02 Figure 2-18. Output Mixers 2.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com The PWM section also contains the power-supply volume control (PSVC) PWM. The interpolator, noise shaper, and PWM sections provide a PWM output with the following features: • Up to 8× oversampling – 8× at FS = 44.1 kHz, 48 kHz, 32 kHz, 38 kHz – 4× at FS = 88.2 kHz, 96 kHz – 2× at FS = 176.4 kHz, 192 kHz • Fifth-order noise shaping • 100-dB dynamic range 0–20 kHz (TAS5508C + TAS5111 system measured at speaker terminals) • THD < 0.
TAS5508C SLES257 – SEPTEMBER 2010 Digital and Power-Supply Gain − dB www.ti.com 30 20 10 Digital Gain 0 −10 −20 −30 Power-Supply Gain −40 −50 −60 −80 −70 −60 −50 −40 −30 −20 −10 0 10 20 30 Desired Gain − dB G002 Figure 2-20. Power-Supply and Digital Gains (Log Space) Digital and Power-Supply Gain − dB 100 10 Digital Gain 1 0.1 Power-Supply Gain 0.01 0.001 0.0001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 Desired Gain − Linear G003 Figure 2-21.
TAS5508C SLES257 – SEPTEMBER 2010 Analog Receiver www.ti.com ADC PCM1802 Audio DSP TAS5508C TAS5111 TAS5111 TAS5111 TAS5111 TAS5111 Audio DSP Provides the Master and Bit Clocks TAS5111 TAS5111 TAS5111 Digital Receiver Audio DSP TAS5508C TAS5111 TAS5111 TAS5111 TAS5111 The Digital Receiver or the Audio DSP Provides the Master and Bit Clocks TAS5111 TAS5111 TAS5111 TAS5111 Figure 2-22.
TAS5508C www.ti.com 3 SLES257 – SEPTEMBER 2010 TAS5508C Controls and Status The TAS5508C provides control and status information from both the I2C registers and device pins. This section describes some of these controls and status functions. The I2C summary and detailed register descriptions are contained in Section 6 and Section 7. 3.1 I2C Status Registers The TAS5508C has two status registers that provide general device information.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com Table 3-1. Device Outputs During Reset (continued) SIGNAL SIGNAL STATE SDA Signal input (not driven) Because RESET is an asynchronous signal, clicks and pops produced during the application (the leading edge) of RESET cannot be avoided. However, the transition from the hard mute state (M) to the operational state is performed using a quiet start-up sequence to minimize noise.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 Table 3-2.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com The crystal time base allows the TAS5508C to determine the CLK rates. Once these rates are determined, the TAS5508C unmutes the audio. 3.2.3 Back-End Error (BKND_ERR) Back-end error is used to provide error management for back-end error conditions. Back-end error is a level-sensitive signal. Back-end error can be initiated by bringing the BKND_ERR terminal low for a minimum 5 MCLK cycles.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 The master mute terminal is used to support a variety of other operations in the TAS5508C, such as setting the interchannel delay, the biquad coefficients, the serial interface format, and the clock rates. A mute command by the master mute terminal, individual I2C mute, the AM interference mute sequence, the bank switch mute sequence, or automute overrides an unmute command or a volume command.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com Table 3-6 lists the optimal setting for each output-stage configuration. Note that the default value is applicable in all configurations except the TAS5182 SE/BTL configuration. Table 3-6.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 Table 3-7. Audio System Configuration (General Control Register 0xE0) Audio System 3.3.3.1 D31–D4 D3 D2 D1 D0 6 channels or 5.1 not using PSVC 0 0 0 1 X 6 channels using PSVC 0 0 1 1 X 5.1 system using PSVC 0 1 1 1 X 8 channels or 7.1 not using PSVC (default) 0 0 0 0 X 8 channels using PSVC 0 0 1 0 X 7.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com Table 3-8. Volume Ramp Rates in ms SAMPLE RATE (kHz) NUMBER OF STEPS 3.3.7 44.1, 88.2, 176.4 32, 48, 96, 192 512 46.44 ms 42.67 ms 1024 92.88 ms 85.33 ms 2048 185.76 ms 170.67 ms Modulation Index Limit PWM modulation is a linear function of the audio signal. When the audio signal is 0, the PWM modulation is 50%. When the audio signal increases toward full scale, the PWM modulation increases toward 100%.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 The MCLK frequency can be 64 × Fs, 128 × Fs, 196 × Fs, 256 × Fs, 384 × Fs, 512 × Fs, or 768 × Fs. The TAS5508C operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK. However, there is no constraint as to the phase relationship of these signals. The TAS5508C accepts a 64 × Fs SCLK rate and a 1 × Fs LRCLK.
TAS5508C SLES257 – SEPTEMBER 2010 3.5.1 www.ti.com Manual Bank Selection The three bank selection bits of the bank control register allow the appropriate bank to be manually selected (000 = bank 1, 001 = bank 2, 010 = bank 3). In the manual mode, when a write occurs to the biquad, DRC, or loudness coefficients, the currently selected bank is updated.
TAS5508C www.ti.com 3.5.5 SLES257 – SEPTEMBER 2010 Bank-Switching Example 1 Problem: The audio unit containing a TAS5508C needs to handle different audio formats with different sample rates. Format #1 requires Fs = 32 kHz, format #2 requires Fs = 44.1 kHz, and format #3 requires Fs = 48 kHz. The sample-rate-dependent parameters in the TAS5508C require different coefficients and data depending on the sample rate.
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TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 4 Electrical Specifications 4.1 Absolute Maximum Ratings (1) Supply voltage, DVDD and DVD_PWM –0.3 V to 3.6 V Supply voltage, AVDD_PLL –0.3 V to 3.6 V 3.3-V digital input Input voltage –0.5 V to DVDD + 0.5 V 5 V tolerant (2) digital input 1.8 V LVCMOS –0.5 V to 6 V (3) –0.5 V to VREF (4) + 0.5 V IIK Input clamp current (VI < 0 or VI > 1.8 V ±20 mA IOK Output clamp current (VO < 0 or VO > 1.
TAS5508C SLES257 – SEPTEMBER 2010 4.5 www.ti.com Electrical Characteristics Over recommended operating conditions (unless otherwise noted) PARAMETER VOH High-level output voltage VOL Low-level output voltage IOZ High-impedance output current TEST CONDITIONS 3.3-V TTL and 5 V (1) tolerant Low-level input current High-level input current 0.5 1.8-V LVCMOS (XTL_OUT) IOL = 0.75 mA 0.5 1.44 3.3-V TTL ±20 (2) VI = VIL ±1 VI = VIL ±1 VI = 0 V, DVDD = 3 V ±1 3.3-V TTL VI = VIH ±1 1.
TAS5508C www.ti.com 4.7.2 SLES257 – SEPTEMBER 2010 Serial Audio Port Serial audio port slave mode over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS fSCLKIN SCLK input frequency CL = 30 pF,SCLK = 64 × Fs MIN TYP 2.048 MAX UNIT 12.
TAS5508C SLES257 – SEPTEMBER 2010 4.7.3 www.ti.com I2C Serial Control Port Operation Timing characteristics for I2C interface signals over recommended operating conditions PARAMETER TEST CONDITIONS MIN fSCL Frequency, SCL tw(H) Pulse duration, SCL high No wait states 0.6 tw(L) Pulse duration, SCL low 1.
TAS5508C www.ti.com 4.7.4 SLES257 – SEPTEMBER 2010 Reset Timing (RESET) Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER tr(DMSTATE) Time to M-STATE low tw(RESET) Pulse duration, RESET active tr(I2C_ready) Time to enable I2C tr(run) Device start-up time MIN TYP 400 MAX UNIT 370 ns None ns 3 ms 10 ms NOTE: Because a crystal time base is used, the system determines the CLK rates.
TAS5508C SLES257 – SEPTEMBER 2010 4.7.6 www.ti.com Back-End Error (BKND_ERR) Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER tw(ER) MIN Pulse duration, BKND_ERR active TYP 350 tp(valid_low) MAX UNIT None ns <100 tp(valid_high) I2C programmable to be between 1 to 10 ms –25 ms 25 % of interval tw(ER) ERR_RCVRY M-State Normal Operation Normal Operation tp(valid_high) tp(valid_low) T0031-01 Figure 4-6. Error Recovery Timing 4.7.
TAS5508C www.ti.com 4.7.8 SLES257 – SEPTEMBER 2010 Headphone Select (HP_SEL) Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER tw(MUTE) Pulse duration, HP_SEL active td(VOL) Soft volume update time t(SW) Switchover time (1) MIN MAX 350 None UNIT ns Defined by rate setting (1) 0.2 ms 1 ms See the Volume Treble and Base Slew Rate Register (0xD0) , Section 7.29.
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TAS5508C www.ti.com 4.8.2 SLES257 – SEPTEMBER 2010 Left-Justified Timing Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 64 × Fs is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock.
TAS5508C SLES257 – SEPTEMBER 2010 4.8.3 www.ti.com Right-Justified Timing Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 64 × Fs is used to clock in the data. The first bit of data appears on the data lines eight bit-clock periods (for 24-bit data) after LRCLK toggles.
TAS5508C www.ti.com 5 SLES257 – SEPTEMBER 2010 I2C Serial-Control Interface (Slave Address 0x36) The TAS5508C has a bidirectional I2C interface that is compatible with the Inter-IC (I2C) bus protocol and supports both 100-kbps and 400-kbps data transfer rates for single- and multiple-byte write and read operations. This is a slave-only device that does not support a multimaster bus environment or wait state insertion.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com During multiple-byte write operations, the TAS5508C compares the number of bytes transmitted to the number of bytes that are required for each specific subaddress. If a write command is received for a biquad subaddress, the TAS5508C expects to receive five 32-bit words. If fewer than five 32-bit data words have been received when a stop command (or another start command) is received, the data received is discarded.
TAS5508C www.ti.com 5.5 SLES257 – SEPTEMBER 2010 Incremental Multiple-Byte Write The I2C supports a special mode which permits I2C write operations to be broken up into multiple data write operations that are multiples of four data bytes. These are 6-byte, 10-byte, 14-byte, 18-byte, etc., write operations that are composed of a device address, read/write bit, subaddress, and any multiple of four bytes of data.
TAS5508C SLES257 – SEPTEMBER 2010 5.7 www.ti.com Multiple-Byte Read A multiple-byte, data-read transfer is identical to a single-byte, data-read transfer except that multiple data bytes are transmitted by the TAS5508C to the master device, as shown in Figure 5-5. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte.
TAS5508C www.ti.com 6 SLES257 – SEPTEMBER 2010 Serial-Control I2C Register Summary The TAS5508C slave address is 0x36. See Serial-Control Interface Register Definitions, Section 7 for complete bit definitions. Note that u indicates unused bits. I2C SUBADDRESS TOTAL BYTES 0x00 1 Clock control register Set data rate and MCLK frequency 1. Fs = 48 kHz 2. MCLK = 256 Fs = 12.
TAS5508C SLES257 – SEPTEMBER 2010 I2C SUBADDRESS TOTAL BYTES 0x41–0x48 32/reg. www.ti.com REGISTER FIELDS DEFAULT STATE Input mixer registers, Ch1–Ch8 8×8 input crossbar mixer setup SDIN1 – SDIN1 – SDIN2 – SDIN2 – SDIN3 – SDIN3 – SDIN4 – SDIN4 – left to input mixer 1 right to input mixer 2 left to input mixer 3 right to input mixer 4 left to input mixer 5 right to input mixer 6 left to input mixer 7 right to input mixer 8 0x49 4 ipmix_1_to_ch8 Input mixer 1 to Ch8 mixer coefficient 0.
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TAS5508C SLES257 – SEPTEMBER 2010 I2C SUBADDRESS TOTAL BYTES www.ti.
TAS5508C www.ti.com 7 SLES257 – SEPTEMBER 2010 Serial-Control Interface Register Definitions Unless otherwise noted, the I2C register default values are in bold font. Note that u indicates unused bits. 7.1 Clock Control Register (0x00) Bit D1 is Don't Care. Table 7-1. Clock Control Register Format D7 D6 D5 D4 D3 D2 0 0 0 – – – – 32-kHz data rate 0 0 1 – – – – 38-kHz data rate 0 1 0 – – – – 44.1-kHz data rate 0 1 1 – – – – 48-kHz data rate 1 0 0 – – – – 88.
TAS5508C SLES257 – SEPTEMBER 2010 7.3 www.ti.com Error Status Register (0x02) Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if there are any persistent errors. Table 7-3.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 Table 7-6.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com Table 7-8. Serial Data Interface Control Register Format (continued) RECEIVE SERIAL DATA INTERFACE FORMAT 7.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 7.10 Automute Control Register (0x14) Table 7-10.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com 7.11 Automute PWM Threshold and Back-End Reset Period Register (0x15) Table 7-11.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 7.12 Modulation Index Limit Register (0x16) Bits D7–D3 are Don't Care. Table 7-12. Modulation Index Limit Register Format D7 D6 D5 D4 D3 D2 D1 D0 LIMIT [DCLKs] MIN WIDTH [DCLKs] MODULATION INDEX 0 0 0 1 2 99.2% 0 0 1 2 4 98.4% 0 1 0 3 6 97.7% 0 1 1 4 8 96.9% 1 0 0 5 10 96.1% 1 0 1 6 12 95.3% 1 1 0 7 14 94.5% 1 1 1 8 16 93.8% 7.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com 7.15 Bank-Switching Command Register (0x40) Bits D31–D24, D22–D19 are Don't Care. Table 7-15.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 Table 7-16.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com Table 7-16.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 Table 7-16.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com 7.17 Bass Management Registers (0x49–0x50) Registers 0x49–0x50 provide configuration control for bass mangement. Each gain coefficient is in 28-bit (5.23) format so 0x80 0000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits not used. Table 7-17.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 Each gain coefficient is in 28-bit (5.23) format so 0x80 0000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits not used. Table 7-19. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass) DESCRIPTION DEFAULT GAIN COEFFICIENT VALUES REGISTER FIELD CONTENTS DECIMAL HEX b0 coefficient u[31:28], b0[27:24], b0[23:16], b0[15:8], b0[7:0] 1.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com 7.21 DRC1 Control Registers, Channels 1–7 (0x96) Bits D31–D14 are Don't Care. Table 7-22.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 7.22 DRC2 Control Register, Channel 8 (0x97) Table 7-23. Channel-8 DRC2 Control Register Format D1 D0 0 D31–D2 0 0 0 Channel 8 (node r): no DRC FUNCTION 0 0 0 1 Channel 8 (node r): pre-volume DRC 0 0 1 0 Channel 8 (node r): post-volume DRC 0 0 1 1 Channel 8 (node r): no DRC 7.23 DRC1 Data Registers (0x98–0x9C) DRC1 applies to channels 1, 2, 3, 4, 5, 6, and 7. Table 7-24.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com 7.24 DRC2 Data Registers (0x9D–0xA1) DRC2 applies to channel 8. Table 7-25.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 Table 7-27.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com Table 7-29.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 Table 7-31.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com 7.29 Volume, Treble, and Bass Slew Rates Register (0xD0) Table 7-33. Volume Gain Update Rate (Slew Rate) D31–D10 D9 D8 0 0 0 512-step update at 4 Fs, 42.6 ms at 48 kHz FUNCTION 0 0 1 1024-step update at 4 Fs, 85.3 ms at 48 kHz 0 1 0 2048-step update at 4 Fs, 170 ms at 48 kHz 0 1 1 2048-step update at 4 Fs, 170 ms at 48 kHz Table 7-34.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 Table 7-36. Master and Individual Volume Controls VOLUME INDEX (H) GAIN/INDEX EXPECTED ACTUAL 001 17.75 17.81 17.81 002 17.5 17.56 17.56 003 17.25 17.31 17.31 004 17 17.06 17.06 005 16.75 16.81 16.81 006 16.5 16.56 16.56 007 16.25 16.31 16.31 008 16 16.05 16.05 009 15.75 15.8 15.8 00A 15.5 15.55 15.55 00B 15.25 15.3 15.3 00C 15 15.05 15.05 00D 14.75 14.8 14.8 00E 14.5 14.55 14.55 00F 14.25 14.3 14.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com 7.31 Bass Filter Set Register (0xDA) Bits D31-D27, D23-D19, D15-D11, and D7-D3 are Don't Care. Table 7-37.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 Table 7-40. Channels 7, 2, and 1 (Center, Right Front, and Left Front) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 0 0 0 0 0 0 0 No change 0 0 0 0 0 0 0 1 Bass filter set 1 0 0 0 0 0 0 1 0 Bass filter set 2 0 0 0 0 0 1 1 1 Bass filter set 3 0 0 0 0 0 1 0 0 Bass filter set 4 0 0 0 0 0 1 0 1 Bass filter set 5 0 0 0 0 0 1 1 0 Reserved 0 0 0 0 0 1 1 1 Reserved 7.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com 7.33 Treble Filter Set Register (0xDC) Bits D31–D27 are Don't Care. Table 7-43.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 Table 7-46. Channels 7, 2, and 1 (Center, Right Front, and Left Front) (continued) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 1 1 Treble filter set 3 FUNCTION 0 0 0 0 0 1 0 0 Treble filter set 4 0 0 0 0 0 1 0 1 Treble filter set 5 0 0 0 0 0 1 1 0 Reserved 0 0 0 0 0 1 1 1 Reserved 7.34 Treble Filter Index (0xDD) Index values above 0x24 are invalid. Table 7-47.
TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com Table 7-49. AM Mode Register Format (continued) D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION 0 – – – – AM mode disabled 1 – – – – AM mode enabled – 0 0 – – Select sequence 1 – 0 1 – – Select sequence 2 – 1 0 – – Select sequence 3 – 1 1 – – Select sequence 4 – – – 0 – IF frequency = 455 kHz – – – 1 – IF frequency = 262.
TAS5508C www.ti.com SLES257 – SEPTEMBER 2010 7.36 PSVC Range Register (0xDF) Bits D31–D2 are zero. Table 7-52. PSVC Range Register Format D31–D2 D1 D0 0 0 0 12.04-dB control range for PSVC FUNCTION 0 0 1 18.06-dB control range for PSVC 0 1 0 24.08-dB control range for PSVC 0 1 1 Ignore – retain last value 7.37 General Control Register (0xE0) Bits D31–D4 are zero. Bit D0 is Don't Care. Table 7-53.
TAS5508C SLES257 – SEPTEMBER 2010 100 www.ti.
TAS5508C www.ti.com 8 SLES257 – SEPTEMBER 2010 TAS5508C Example Application Schematic The following page contains an example application schematic for the TAS5508C.
5 4 3 2 1 V-HBRIDGE +3.3V +5.0V /SD2_TAS5121 Left + Right Line Out /LINE_OUT_ENABLE /OTW_TAS5121 /SD1_TAS5121 GVDD V-HBRIDGE /TEMP_WARNING GVDD +5.0V PWM_P_R PWM_P +3.3V PWM_M_R Phono socket J950 LINE OUTPUT 4 3 2 1 /OE OUT_R /VALID OUT_1 1 OUT_2 2 J600 PWM_M_L RIGHT BACK SURROUND SPEAKER OUTPUT CH6 TAS5121 H-Bridge Output Stage PWM_P_L Phono socket J951 D PWM_M /VALID_CH5+CH6 4 3 2 1 V-HBRIDGE OUT_L /SD2_TAS5121 2 Channel Line Out (TLV272) /OTW_TAS5121 GND +5.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS5508CPAGR Package Package Pins Type Drawing TQFP PAG 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1500 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 1.5 16.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5508CPAGR TQFP PAG 64 1500 367.0 367.0 45.
MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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