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2.4 Digital Audio Interface (J60)
Digital Audio Interface (J60)
The digital audio interface contains digital audio signal data (I
2
S), clocks, etc. Please see the TAS5504A
Data Manual for signal timing and details not explained in this document.
Table 2-5. J60 Pin Description
PIN NET NAME
DESCRIPTION
NO. AT SCHEMATICS
1 GND Ground
2 MCLK Master clock input. Low-jitter system clock for PWM generation and
reclocking. Ground connection from source to TAS5504A must be a
low impedance connection.
3 GND Ground
4 SDIN1 I
2
S data 1, channel 1 and 2
5 SDIN2 I
2
S data 2, channel 3 and 4
6 SDIN3 I
2
S data 3
7 SDIN4 I
2
S data 4
8 Reserved
9 Reserved
10 GND Ground
11 SCLK I
2
S bit clock
12 GND Ground
13 LRCLK I
2
S left-right clock
14 GND Ground
15 Reserved
16 GND Ground
SLEU075 – June 2006 – Revised June 2006 System Interfaces 15
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