Datasheet

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ELECTRICAL CHARACTERISTICS
TAS5352
SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007
PVDD_x = 34.5 V, GVDD_X = 12 V, VDD = 12 V, T
C
(Case temperature) = 75 ° C, f
S
= 384 kHz, unless otherwise specified.
TAS5352
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
Internal Voltage Regulator and Current Consumption
Voltage regulator, only used as a
VREG VDD = 12 V 3 3.3 3.6 V
reference node
Operating, 50% duty cycle 7.2 17
IVDD VDD supply current mA
Idle, reset mode 5.5 11
50% duty cycle 8 16
IGVDD_X Gate supply current per half-bridge mA
Reset mode 1 1.8
50% duty cycle, without output filter or load 13.6 25 mA
IPVDD_X Half-bridge idle current
Reset mode, no switching 525 630 μ A
Output Stage MOSFETs
Drain-to-source resistance, Low
R
DSon,LS
T
J
= 25 ° C, excludes metallization resistance, 80 89 m Ω
Side
Drain-to-source resistance, High
R
DSon,HS
T
J
= 25 ° C, excludes metallization resistance, 80 89 m Ω
Side
I/O Protection
Undervoltage protection limit,
V
uvp,G
9.5 V
GVDD_X
V
uvp,hyst
(1)
Undervoltage protection limit, 250 mV
GVDD_X
BST
uvpF
Puts device into RESET when BST 5.9 V
voltage falls below limit
BST
uvpR
Brings device out of RESET when 7 V
BST voltage rises above limit
OTW
(1)
Overtemperature warning 115 125 135 ° C
Temperature drop needed below
OTW
HYST
(1)
OTW temp. for OTW to be inactive 25 ° C
after the OTW event
OTE
(1)
Overtemperature error threshold 145 155 165 ° C
OTE- OTE - OTW differential, temperature
30 ° C
OTW
differential
(1)
delta between OTW and OTE
OLPC Overload protection counter f
S
= 384 kHz 1.25 ms
Resistor — programmable, high-end,
I
OC
Overcurrent limit protection 10.9 A
R
OC
= 22 k Ω with 1 mS pulse
I
OCT
Overcurrent response time 150 ns
t
ACTIVITY
Time for PWM activity detector to
Lack of transistion of any PWM input 13.2 μ S
DETECTOR
activite when no PWM is present
Connected when RESET is active to provide
Output pulldown current of each
I
PD
bootstrap capacitor charge. Not used in SE 3 mA
half-bridge
mode.
Static Digital Specifications
V
IH
High-level input voltage 2 V
PWM_A, PWM_B, PWM_C, PWM_D, M1,
M2, M3, RESET_AB, RESET_CD
V
IL
Low-level input voltage 0.8 V
I
Leakage
Input leakage current 100 μ A
OTW/SHUTDOWN (SD)
Internal pullup resistance, OTW to
R
INT_PU
20 26 32 k Ω
VREG, SD to VREG
Internal pullup resistor 3 3.3 3.6
V
OH
High-level output voltage V
External pullup of 4.7 k Ω to 5 V 4.5 5
V
OL
Low-level output voltage I
O
= 4 mA 0.2 0.4 V
(1) Specified by design
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