Datasheet

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Overtemperature Protection
DEVICE RESET
Undervoltage Protection (UVP) and Power-On
TAS5352
SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007
The TAS5352 has a two-level temperature-protection
Two reset pins are provided for independent control
system that asserts an active-low warning signal
of half-bridges A/B and C/D. When RESET_AB is
( OTW) when the device junction temperature
asserted low, all four power-stage FETs in half--
exceeds 125 ° C (typical) and, if the device junction
bridges A and B are forced into a high-impedance
temperature exceeds 155 ° C (typical), the device is
(Hi-Z) state. Likewise, asserting RESET_CD low
put into thermal shutdown, resulting in all half-bridge
forces all four power-stage FETs in half-bridges C
outputs being set in the high-impedance (Hi-Z) state
and D into a high-impedance state. Thus, both reset
and SD being asserted low. OTE is latched in this
pins are well suited for hard-muting the power stage if
case. To clear the OTE latch, either RESET_AB or
needed.
RESET_CD must be asserted. Thereafter, the device
In BTL modes, to accommodate bootstrap charging
resumes normal operation.
prior to switching start, asserting the reset inputs low
enables weak pulldown of the half-bridge outputs. In
the SE mode, the weak pulldowns are not enabled,
Reset (POR)
and it is therefore recommended to ensure bootstrap
The UVP and POR circuits of the TAS5352 fully
capacitor charging by providing a low pulse on the
protect the device in any power-up/down and
PWM inputs when reset is asserted high.
brownout situation. While powering up, the POR
Asserting either reset input low removes any fault
circuit resets the overload circuit (OLP) and ensures
information to be signalled on the SD output, i.e., SD
that all circuits are fully operational when the
is forced high.
GVDD_X and VDD supply voltages reach stated in
the Electrical Characteristics Table. Although
A rising-edge transition on either reset input allows
GVDD_X and VDD are independently monitored, a
the device to resume operation after an overload
supply voltage drop below the UVP threshold on any
fault. To ensure thermal reliability, the rising edge of
VDD or GVDD_X pin results in all half-bridge outputs
reset must occur no sooner than 4 ms after the falling
immediately being set in the high-impedance (Hi-Z)
edge of SD.
state and SD being asserted low. The device
automatically resumes operation when all supply
voltages have increased above the UVP threshold.
22 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TAS5352