Datasheet

www.ti.com
ELECTRICAL CHARACTERISTICS
TAS5261
SLES188 – AUGUST 2006
Audio frequency = 1 kHz, PVDD_x = 50 V, GVDDx = 12 V, VDD = 12 V, R
L
= 8 Ω , f
s
= 384 kHz, OC_ADJ = 22 k Ω ,
T
C
= 75 ° C, output filter is L
DEM
= 10 µ H, C
L
= 1 µ F (unless otherwise noted). AC performance is recorded as a chipset,
TAS5518 as front end with an effective modulation index of 96.1% and TAS5261 as the power stage. PCB and system
configuration are in accordance with recommended design guidelines.
PARAMETER CONDITIONS MIN TYP MAX UNIT
Internal Voltage Regulator and Current Consumption
Voltage regulator,
VREG 3.3 V
only used as reference node
Operating, 50% duty cycle 7.7
I
VDD
VDD supply current mA
Idle, reset mode 6.7
50% duty cycle 15
GVDD_x gate-supply current
I
GVDD_x
mA
per half bridge
Idle, reset mode 1.5
50% duty cycle 23 mA
I
PVDD_x
Half-bridge idle current
Reset mode ( RESET = 1),
100 µ A
No switching
Output-Stage MOSFETs
R
DSON,LS
Drain-to-source resistance, low side T
J
= 25 ° C, LDMOS only 40 m Ω
R
DSON,HS
Drain-to-source resistance, high side T
J
= 25 ° C, LDMOS only 40 m Ω
I/O Protection
V
UVP,POS
Undervoltage protection limit, GVDD_x 8.5 V
OTW Overtemperature warning 125 ° C
OTW
hys
OTW hysteresis 25 ° C
OTE Overtemperature error threshold 155 ° C
OTE
hys
OTE hysteresis 30 ° C
OTE-OTW
Temperature delta between OTW and OTE 30 ° C
differential
OLPC Overload protection time constant f
PWM
= 384 kHz 20 ms
Resistor programmable high end
I
OC
Overcurrent limit response
(1)
15 16 17 A
with OC_ADJ = 22 k Ω
(1)
R
OC
Programming resistor 22 100 k Ω
Connected when RESET is high to
Pulldown resistor at the output of each
R
PD
provide a charge path for the 2.5 k Ω
half-bridge
bootstrap capacitor
PWM PWM Activity Detector Lack of transition of any PWM input 13 µ s
(1) DC measurement with 1-ms pulse
9
Submit Documentation Feedback