Datasheet

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TEMP
SENSE
M1
M2
AGND
OC_
ADJ
VREG VREG
VDD
GVDD
_B
M3
P
OWER
-
UP
R
ESET
U
VP
GND
PWM
_B
OUT
_
B
(x3)
PGND
(x3)
PVDD
_
B
(x3)
BST_B
TIMING
CONTROL
GATE
-
DRIVECONTROL
PWM
RECEIVER
OVER
-
LOAD
PROT
.
GVDD
_A
PWM
ACTIVITY
DETECTOR
CB
3C
GVDD
_B
CURRENT
SENSE
GVDD
_A
PWM
_A
OUT
_A
(
x3)
PGND
(x3)
PVDD
_A
(
x3)
BST_A
TIMING
CONTROL
CONTROL GATE
-
DRIVE
PWM
RECEIVER
PROTECTION & I/O LOGIC
OTW
SD
RESET
TAS5261
SLES188 – AUGUST 2006
Figure 2. Functional Block Diagram
6
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