Datasheet

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B0101-01
PVDD(0–50V)
Mono
BTL
H-Bridge
Hardwire
Mode
Control
Hardwire
Mode
Control
M1
M1
M2
M2
M3
M3
System
Microcontroller
RESET_H-Bridge
SD
OTW
OTW
SD
RESET
Hardwire
Over-
current
Limit
Hardwire
Over-
current
Limit
PVDD
Power-Supply
Decoupling
PVDD
Power-Supply
Decoupling
GVDD,VDD,
andVREG
Power-Supply
Decoupling
GVDD,VDD,
andVREG
Power-Supply
Decoupling
6
6
6
6
2
2
GVDD(12V)andVDD(12V)
GVDD(12V)andVDD(12V)
GND
GND
PVDD(0–50V)
System
Power
Supplies
50V
12V
GND
AC
Bootstrap
Capacitors
Bootstrap
Capacitors
BST_A
BST_A
BST_B
BST_B
R2
L2
PWM_B
RESET
Shutdown
Overtemp_warning
R1
L1
TAS55XX
Left
Output
Right
Output
PWM_A
H-Bridge
Output
H-Bridge
Output
PVDD_A,B
VDD
VREG
GND
GND
GVDD_A,B
GND_A,B
OC_ADJ
Mono
BTL
H-Bridge
PWM_B
RESET
Shutdown
Overtemp_warning
PWM_A
PVDD_A,B VDD
VREG
GND GND
GVDD_A,B GND_A,B OC_ADJ
2nd-Order
L-COutput
Filterfor
Each
H-Bridge
2nd-Order
L-COutput
Filterfor
Each
H-Bridge
OUT_A
OUT_A
OUT_B
OUT_B
4–8
(3 Min)
W
W
4–8
(3 Min)
W
W
TAS5261
SLES188 – AUGUST 2006
Figure 1. Typical System Block Diagram
5
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