Datasheet

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ELECTRICAL CHARACTERISTICS
TAS5186A
SLES156 – OCTOBER 2005
F
PWM
= 384 kHz, GVDD = 12 V, VDD = 12 V, T
C
(case temperature) = 75 ° C, unless otherwise noted. All performance is in
accordance with recommended operating conditions, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG Voltage regulator, only used as reference node VDD = 12 V 3 3.3 3.6 V
Operating, 50% duty cycle 7 20
IVDD VDD supply current mA
Idle, reset mode 6 16
50% duty cycle 5 22
IGVDD_X Gate supply current per half-bridge mA
Idle, reset mode 1 3
50% duty cycle, without output filter or load, 5.1
110
mode. 22- µ H Kwang-Sung inductors
IPVDD_X Half-bridge idle current mA
50% duty cycle, without output filter or load, 2.1
60
mode. 22- µ H Kwang-Sung inductors
OUTPUT STAGE MOSFETs
R
DSon
, LS Sat Drain-to-source resistance, low side, satellite T
J
= 25°C, includes metallization resistance 210 m Ω
R
DSon
, HS Sat Drain-to-source resistance, high side, satellite T
J
= 25°C, includes metallization resistance 210 m Ω
R
Dson
, LS Sub Drain-to-source resistance, low side, subwoofer T
J
= 25°C, includes metallization resistance 110 m Ω
R
Dson
, HS Sub Drain-to-source resistance, high side, subwoofer T
J
= 25°C, includes metallization resistance 110 m Ω
I/O PROTECTION
V
UVP, G
Undervoltage protection limit GVDD_X 10 V
V
UVP, hyst
(1)
Undervoltage protection hysteresis 250 mV
OTW
(1)
Overtemperature warning 125 °C
Temperature drop needed below OTW temp. for
OTW
hyst
(1)
25 °C
OTW to be inactive after the OTW event
OTE
(1)
Overtemperature error 155 °C
Temperature drop needed below OTE temp. for SD
OTE
HYST
(1)
25 °C
to be released after the OTE event
OLCP Overload protection counter 1.25 ms
Overcurrent limit protection, satellite Rocp = 18 k Ω 4.5 A
I
OC
Overcurrent limit protection, subwoofer Rocp = 18 k Ω 8 A
I
OCT
Overcurrent response time 210 ns
Rocp OC programming resistor range Resistor tolerance = 5% 18 k Ω
STATIC DIGITAL SPECIFICATION
V
IH
High-level input voltage 2
PWM_X, M1, M2, M3, RESET V
V
IL
Low-level input voltage 0.8
I
LEAK
Input leakage current Static condition –80 80 µ A
OTW/SHUTDOWN (SD)
Internal pullup resistor to DREG (3.3 V) for SD and
R
INT_PU
26 k Ω
OTW
Internal pullup resistor only 3 3.3 3.6
V
OH
High-level output voltage
External pullup: 4.7-k Ω resistor to 5 V 4.5 5 V
V
OL
Low-level output voltage I
O
= 4 mA 0.2 0.4
FANOUT Device fanout OTW, SD No external pullup 30 Devices
(1) Specified by design.
7