Datasheet

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M1
M2
RESET
SD
OTW
AGND
OC_ADJ
VREG VREG
VDD
GVDD_DEF
M3
Undervoltage
Protection
GND
PWM_F OUT_F
PGND
PVDD_F
BST_F
PWM
Receiver
I
Sense
Protection
and
I/O Logic
Power-On
Reset
Temperature
Sense
Overload
Protection
Control Timing
Gate
Drive
PWM_E OUT_E
PGND
PVDD_E
BST_E
PWM
Receiver
Control Timing
Gate
Drive
PWM_D OUT_D
PGND
PVDD_D
BST_D
PWM
Receiver
Control Timing
Gate
Drive
PWM_C OUT_C
PGND
PVDD_C
BST_C
PWM
Receiver
Control Timing
Gate
Drive
PWM_B OUT_B
PGND
PVDD_B
BST_B
PWM
Receiver
Control Timing
Gate
Drive
PWM_A OUT_A
PVDD_A
BST_A
PWM
Receiver
Control Timing
Gate
Drive
OUT_BIAS
BST_BIAS
Control Timing
Gate
Drive
B0034-03
Internal Pullup
Resistors to VREG
GVDD_ABC
TAS5186A
SLES156 – OCTOBER 2005
TYPICAL SYSTEM DIAGRAM
A schematic diagram for a typical system is appended at the end of the data sheet.
FUNCTIONAL BLOCK DIAGRAM
5