Datasheet

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Overtemperature Protection
UNDERVOLTAGE PROTECTION (UVP) AND
DEVICE RESET
ACTIVE-BIAS CONTROL (ABC)
TAS5186A
SLES156 – OCTOBER 2005
element in the audio path, i.e., split-cap capacitors or
series capacitor, to the desired potential before
The TAS5186A has a two-level
switching is started on the PWM outputs. (For
temperature-protection system that asserts an
recommended configuration, see the typical
active-low warning signal ( OTW) when the device
application schematic included in this data sheet).
junction temperature exceeds 125°C (typical), and If
the device junction temperature exceeds 155°C The start-up sequence can be controlled through
(typical), the device is put into thermal shutdown, sequencing the M3 and RESET pins according to
resulting in all half-bridge outputs being set in the Table 2 and Table 3 .
high-impedance state (Hi-Z) and SD being asserted
low. Table 2. 5.1 Mode—All Output Channels Active
M3 RESET OUT_BIAS OUT_A, OUT_D, COMMENT
_B, _C _E, _F
POWER-ON RESET (POR)
0 0 Hi-Z Hi-Z Hi-Z All outputs
disabled,
The UVP and POR circuits of the TAS5186A fully
nothing is
protect the device in any power-up/down and
switching.
brownout situation. While powering up, the POR
1 0 Active Hi-Z Hi-Z OUT_BIAS
circuit resets the overload circuit (OLP) and ensures
enabled, all
that all circuits are fully operational when the
other outputs
disabled
GVDD_X and VDD supply voltages reach 10 V
(typical). Although GVDD_X and VDD are
1 1 Hi-Z Active Active OUT_BIAS
disabled, all
independently monitored, a supply voltage drop
other outputs
below the UVP threshold on any VDD or GVDD_X
switching
pin results in all half-bridge outputs immediately being
set in the high-impedance (Hi-Z) state and SD being
Table 3. 2.1 Mode—Only Output Channels A, B,
asserted low. The device automatically resumes
and C Active
operation when all supply voltages have increased
above the UVP threshold.
M3 RESET OUT_BIAS OUT_A, OUT_D, COMMENT
_B, _C _E, _F
0 0 Hi-Z Hi-Z Hi-Z All outputs
disabled,
When RESET is asserted low, the output FETs in all
nothing is
half-bridges are forced into a high-impedance (Hi-Z)
switching.
state.
1 0 Active Hi-Z Hi-Z OUT_BIAS
enabled, all
Asserting the RESET input low removes any fault
other outputs
information to be signaled on the SD output, i.e., SD
disabled
is forced high.
0 1 Hi-Z Active Hi-Z OUT_BIAS
disabled, all
A rising-edge transition on the RESET input allows
other outputs
the device to resume operation after an overload
switching
fault.
When the TAS5186A is used with the TAS5086 PWM
modulator, no special attention to start-up sequencing
is required, provided that the chipset is configured as
Audible pop noises are often associated with
recommended.
single-rail, single-ended power stages at power-up or
at the start of switching. This commonly known
problem has been virtually eliminated by
incorporating a proprietary active-bias control circuitry
as part of the TAS5186A feature set. By the use of
only a few passive external components (typically
resistors), the ABC can pre-charge the dc-blocking
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