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OVERTEMPERATURE PROTECTION
ACTIVE-BIAS CONTROL (ABC)
THERMAL CONSIDERATIONS
UNDERVOLTAGE PROTECTION (UVP) AND
DEVICE RESET
TAS5176
SLES196 – JUNE 2007
A rising-edge transition on the RESET input allows
the device to resume operation after an overload
The TAS5176 has a two-level temperature-protection
fault.
system that asserts an active-low warning signal
( OTW) when the device junction temperature
exceeds 125 ° C (typical), and If the device junction
temperature exceeds 155 ° C (typical), the device is
Audible pop noises are often associated with
put into thermal shutdown, resulting in all half-bridge
single-rail, single-ended power stages at power-up or
outputs being set in the high-impedance state (Hi-Z)
at the start of switching. This commonly known
and SD being asserted low.
problem has been virtually eliminated by
incorporating a proprietary active-bias control
circuitry as part of the TAS5176 feature set. By the
use of only a few passive external components
The TAS5176 device package (DDW) is designed
(typically resistors), the ABC can pre-charge the
with the PowerPad on the bottom of the device. It
dc-blocking element in the audio path, i.e., split-cap
must be soldered to the ground plane on the printed
capacitors or series capacitor, to the desired
circuit board (PCB). Under the PowerPad, there
potential before switching is started on the PWM
should be a pattern of vias to conduct heat through
outputs. (For recommended configuration, see the
the PCB to the bottom layer ground plane. Using this
typical application schematic included in this data
technique alone, the device is capable of a total
sheet).
continuous power of 80 Watts.
The start-up sequence can be controlled through
Additional heatsinking is required for total continuous
sequencing the M3 and RESET pins according to
power of 100 Watts. An exposed area in the bottom
Table 2 and Table 3 .
layer soldermask can be created and then a
aluminum bracket mechanically and thermally
Table 2. 5.1 Mode—All Output Channels Active
coupled (with heatsink paste) to the exposed area.
M3 RESET OUT_BIAS OUT_A, OUT_D, COMMENT
The other end of the aluminum bracket can then be
_B, _C _E, _F
mechanically and thermally connected to the system
0 0 Hi-Z Hi-Z Hi-Z All outputs
chassis. This technique will allow the TAS5176 to
disabled,
run at higher ambient temperatures and/or deliver
nothing is
more power.
switching.
1 0 Active Hi-Z Hi-Z OUT_BIAS
enabled, all
POWER-ON RESET (POR)
other outputs
disabled
The UVP and POR circuits of the TAS5176 fully
1 1 Hi-Z Active Active OUT_BIAS
protect the device in any power-up/down and
disabled, all
brownout situation. While powering up, the POR
other outputs
circuit resets the overload circuit (OLP) and ensures
switching
that all circuits are fully operational when the
GVDD_X and VDD supply voltages reach 10 V
Table 3. 2.1 Mode—Only Output Channels A, B,
(typical). Although GVDD_X and VDD are
and C Active
independently monitored, a supply voltage drop
M3 RESET OUT_BIAS OUT_A, OUT_D, COMMENT
below the UVP threshold on any VDD or GVDD_X
_B, _C _E, _F
pin results in all half-bridge outputs immediately
0 0 Hi-Z Hi-Z Hi-Z All outputs
being set in the high-impedance (Hi-Z) state and SD
disabled,
being asserted low. The device automatically
nothing is
resumes operation when all supply voltages have
switching.
increased above the UVP threshold.
1 0 Active Hi-Z Hi-Z OUT_BIAS
enabled, all
other outputs
disabled
When RESET is asserted low, the output FETs in all
0 1 Hi-Z Active Hi-Z OUT_BIAS
half-bridges are forced into a high-impedance (Hi-Z)
disabled, all
state. other outputs
switching
Asserting the RESET input low removes any fault
information to be signaled on the SD output, i.e., SD
is forced high.
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