Datasheet

www.ti.com
THEORY OF OPERATION
POWER SUPPLIES
SYSTEM POWER-UP/DOWN SEQUENCE
Powering Down
Error Reporting
TAS5176
SLES196 – JUNE 2007
reliability it is important that each PVDD_X pin is
decoupled with a 100-nF ceramic capacitor placed
as close as possible to each supply pin on the same
To facilitate system design, the TAS5176 needs only
side of the PCB as the TAS5176. It is recommended
a 12-V supply in addition to a typical 31-V
to follow the PCB layout and PowerPad layout of the
power-stage supply. An internal voltage regulator
TAS5176 reference design. For additional
provides suitable voltage levels for the digital and
information on the recommended power supply and
low-voltage analog circuitry. Additionally, all circuitry
required components, see the application diagrams
requiring a floating voltage supply, e.g., the high-side
given in this data sheet. The 12-V supply should be
gate drive, is accommodated by built-in bootstrap
powered from a low-noise, low-output-impedance
circuitry requiring only a few external capacitors.
voltage regulator. Likewise, the PVDD power-stage
supply is assumed to have low output impedance
In order to provide outstanding electrical and
and low noise. The power-supply sequence is not
acoustic characteristics, the PWM signal path
critical due to the internal power-on-reset circuit.
including gate drive and output stage is designed as
Moreover, the TAS5176 is fully protected against
identical, independent half-bridges. For this reason,
erroneous power-stage turnon due to parasitic gate
each half-bridge has separate bootstrap pins
charging. Thus, voltage-supply ramp rates (dv/dt) are
(BST_X) and power-stage supply pins (PVDD_X).
typically noncritical.
Furthermore, an additional pin (VDD) is provided as
power supply for all common circuits. Although
supplied from the same 12-V source, it is highly
recommended to separate GVDD_X and VDD on the
The TAS5176 does not require a power-up
printed-circuit board (PCB) by RC filters (see
sequence. The outputs of the H-bridge remain in a
application diagram for details). These RC filters
high-impedance state until the gate-drive supply
provide the recommended high-frequency isolation.
voltage (GVDD_X) and VDD voltage are above the
Special attention should be paid to placing all
undervoltage protection (UVP) voltage threshold (see
decoupling capacitors as close to their associated
the Electrical Characteristics section of this data
pins as possible. In general, inductance between the
sheet). Although not specifically required, it is
power-supply pins and decoupling capacitors must
recommended to hold RESET in a low state while
be avoided. (See reference board documentation for
powering up the device.
additional information.)
When the TAS5176 is being used with TI PWM
For a properly functioning bootstrap circuit, a small
modulators such as the TAS5086, no special
ceramic capacitor must be connected from each
attention to the state of RESET is required, provided
bootstrap pin (BST_X) to the power-stage output pin
that the chipset is configured as recommended.
(OUT_X). When the power-stage output is low, the
bootstrap capacitor is charged through an internal
diode connected between the gate-drive
power-supply pin (GVDD_X) and the bootstrap pin. The TAS5176 does not require a power-down
When the power-stage output voltage is high, the sequence. The device remains fully operational as
bootstrap capacitor voltage is shifted above the long as the gate-drive supply (GVDD_X) voltage and
output voltage potential and thus provides a suitable VDD voltage are above the undervoltage protection
voltage supply for the high-side gate driver. In an (UVP) threshold level (see the Electrical
application with PWM switching frequencies in the Characteristics section of this data sheet). Although
range 352 kHz to 384 kHz, it is recommended to use not specifically required, it is a good practice to hold
33-nF ceramic capacitors, size 0603 or 0805, for the RESET low during power down, thus preventing
bootstrap capacitor. These 33-nF capacitors ensure audible artifacts including pops and clicks
sufficient energy storage, even during minimal PWM
When the TAS5176 is being used with TI PWM
duty cycles, to keep the high-side power stage FET
modulators such as the TAS5086, no special
(LDMOS) fully started during all of the remaining part
attention to the state of RESET is required, provided
of the PWM cycle. In an application running at a
that the chipset is configured as recommended.
reduced switching frequency, generally 250 kHz to
192 kHz, the bootstrap capacitor might need to be
increased in value. Special attention should be paid
to the power-stage power supply; this includes
The SD and OTW pins are both active-low,
component selection, PCB placement and routing.
open-drain outputs. Their function is for
As indicated, each half-bridge has independent
protection-mode signaling to a PWM controller or
power-stage supply pins (PVDD_X). For optimal
other system-control device.
electrical performance, EMI compliance, and system
16
Submit Documentation Feedback