Datasheet

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1.2 PCB Key Map
SPEAKEROUTPUTS
T
I
4-CHANNEL SE
POWERSTAGE
T
AS5162
INPUT SIGNAL
INTERFACE (J60)
CONTROL
INTERFACE (
J
40
)
J101 J102 J103 J104 J105 J106
TAS5086
3.3-V
Regulator
2-CHANNEL BTL
POWERSTAGE
TAS5162
5-V
Regulator
GateDrive
Regulator
PSU
INTERFACE
(J901+J902)
2 Quick-Setup Guide
2.1 Electrostatic Discharge Warning
Quick-Setup Guide
Physical structure for the TAS5162DDV6EVM is illustrated in Figure 3 .
Figure 3. Physical structure for the TAS5162DDV6EVM (Approximate Layout)
This section describes the TAS5162DDV6EVM board in regards to power supplies and system interfaces.
The section provides information regarding handling and unpacking, absolute operating conditions, and a
description of the factory default switch and jumper configuration.
This section provides a step–by–step guide to configuring the TAS5162DDV6EVM for device evaluation.
Many of the components on the TAS5162DDV6EVM are susceptible to damage by electrostatic discharge
(ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handling
the EVM, including the use of a grounded wrist strap at an approved ESD workstation.
CAUTION
Failure to observe ESD handling procedures may result in damage to EVM
components.
SLAU230A – September 2007 – Revised October 2007 TAS5162DDV6EVM 5
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