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Appendix A Design Documents
A.1 HLP_MC012 Schematic
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1
1
1
0
0
0
0
1
1
0
0
1
0
1
I
I
O
O
O
O
O
1
0
0
1
0
0
1
1
NC
4
1
0
O
FROM
MATING
7
6
5
0
3
1
2
1
0
1
0
1
1
0
L/H
H/L
L/H
H/L
H/L
H/L
H/L
3.3V
64fs
64fs
64fs
64fs
64fs
I
I
O
O
O
O
O
SET
TO
SET TO
OCKS1
NC
NC
Xtal
512fs
256fs
256fs
128fs
1
54kHz
108kHz
fs(MAX)
108kHz
216kHz
LDN
MODE
4
DIF1
0
H/L
I/O
64fs
I/O
O
I2S
CONTROLLERFOR TAS5132DDV2EVM
OPTICAL INPUT
RCA INPUT
SUPPLY
64-128fs
64-128fs
24Bit/I2S
24Bit/LJ
24Bit/I2S
16Bit/RJ
24Bit/RJ
18Bit/RJ
20Bit/RJ
LRCK BICK/BCK
RESET
FROM
CONTROL
256/256/108
OCKS0
ThuFeb15,2007
I2SOUT
512fs
256fs
256fs
MCLK01
128fs
CONNECT
OR
DIF2
DIF0
POWER
SWITCHING
L/R
LRCK
SDTO/DATA
24Bit/LJ
U5
AK4113VF
HPL-MC012.sch
DECEMBER72006
SPDIFLock
AUDIOSERIAL INTERFACEFORMA
T
FREDSHIPLEY
MASTERCLOCKOUTPUT
FREQUENCY
SPDIF/3.3VSWITCHINGPOWERSUPPL
Y
SLLU097 – April 2007 Design Documents 13
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