Datasheet

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THEORY OF OPERATION

POWER SUPPLIES

Recommendations for Powering Up

RESET

GVDD

PVDD_X

PWM_xP

> 1 ms

TAS5121I

SLES122 – SEPTEMBER 2004

This power device requires only two power supply voltages: GVDD_x and PVDD_x.

GVDD_x is the gate drive supply for the device, which is usually supplied from an external 12-V power supply.

GVDD_x is also connected to an internal LDR that regulates the GVDD_x voltage down to the logic power

supply, 3.3 V, for the TAS5121I internal logic blocks. Each GVDD_x pin is decoupled to system ground by a 1- µ F

capacitor.

PVDD_x is the H-bridge power supply. Two power pins are provided for each half-bridge due to the high current

density. It is important to follow the circuit and PCB layout recommendations for the design of the PVDD_x

connection. For component suggestions, see the Typical Application Configuration Used With TAS5026 PWM

Processor section in this document. Following these recommendations is important because they influence key

system parameters such as EMI, idle current, and audio performance.

When GVDD_x is applied, while RESET is held low, the error latches are cleared, SHUTDOWN is set high, and

the outputs are held in a high-impedance state. The bootstrap (BST) capacitor is charged by the current path

through the internal BST diode and external resistors placed on the PCB from each OUT_x pin to ground.

Ideally, PVDD_x is applied after GVDD_x. When GVDD_x and PVDD_x are applied, the TAS5121I is ready for

operation. PWM input signals can then be applied any time during the power-on sequence, but they must be

active and stable before RESET is set high.

Table 1 describes the input conditions and the output states of the device.

Table 1. Input/Output States

INPUTS OUTPUTS

CONDITION

DESCRIPTION

RESET PWM_AP PWM_BP SHUTDOWN OUT_A OUT_B

X X X 0 Hi-Z Hi-Z Shutdown

0 X X 1 Hi-Z Hi-Z Reset

1 0 0 1 GND GND

1 0 0 1 PVDD PVDD Normal

1 0 1 1 GND PVDD Normal

1 1 1 1 PVDD PVDD Reserved

After the previously mentioned conditions are met, the device output begins. If PWM_AP is equal to a high and

PMW_BP is equal to a low, the high-side MOSFET in the A half-bridge of the output H-bridge conducts while the