Datasheet

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TYPICAL APPLICATION CONFIGURATION USED WITH TAS5026 PWM PROCESSOR
TAS5121IDKD
21
20
5
14
12
11
10
9
8
GVDD_B
OUT_A
GND
PVDD_A
GND
PVDD_B
PVDD_B
PVDD_A
OUT_B
31
32
34
BST_B
OUT_B
33
GND
OUT_A
35
30
28
26
29
27
BST_A
GND
GVDD_A
23
25
22
24
7
15
16
17
13
6
2
3
4
10 µH
10 µH
4.7 kΩ
1000 µF
PWM_AP_1
PWM_BP_1
1 µF
100
nF
100 Ω
2.7 Ω
2.7 Ω
100 nF
33 nF
100 nF
33 nF
1 µF
100 nF
H-Bridge
Power Supply
Gate-Drive
Power Supply
4.7 kΩ
75 nH L
PCB
‡
PWM_AP
GVDD
GND
M2
M1
DREG
M3
DGND
RESET
OTW
DGND
SD
DVDD
DREG_RTN
GND
PWM_BP
1 Ω
1 Ω
1
GND
GVDD_B
36
18
GND
19
GVDD_A
†
Voltage suppressor diodes: 1SMA33CAT3
‡
L
PCB
: Track in the PCB (1 mm wide and 50 mm long)
22 Ω
33 µF
1 µF
TVS Zener
†
TVS Zener
†
22 Ω
1 µF
75 nH L
PCB
‡
1 µF
Micro-
controller
S0015−01
TAS5121I
SLES122 – SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
PVDD_X = 30.5 V, GVDD_x = 12 V, DVDD connected to DREG via a 100- Ω resistor, R
L
= 4 Ω , 8X f
s
= 384 kHz, TAS5026
PWM processor, unless otherwise noted
TYPICAL OVER TEMPERATURE
SYMBOL PARAMETER TEST CONDITIONS
T
Case
= MIN/TYP/
T
A
=25 ° C T
A
=25 ° C UNITS
75 ° C MAX
STATIC DIGITAL INPUT SPECIFICATION, PWM, PROTECTION MODE SELECTION PINS, AND OUTPUT MODE SELECTION PINS
2 V Min
V
IH
High-level input voltage
DVDD V Max
V
IL
Low-level input voltage 0.8 V Max
–10 µ A Min
Leakage Input leakage current
10 µ A Max
OTW/SHUTDOWN (SD)
Internal pullup resistor from OTW
32 22 k Ω Min
and SD to DVDD
V
OL
Low-level output voltage I
O
= 1 mA 0.4 V Max
6