Datasheet

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Protection
Logic
OT
and
UVP
GVDD
DREG
DREG_RTN
PWM
Receiver
Timing
Control
and
Protection
Gate
Drive
Gate
Drive
PWM_AP OUT_A
GND
PVDD_A
BST_A
DREG
GVDD_A
OCH
OCL
Timing
Control
and
Protection
Gate
Drive
Gate
Drive
PWM_BP OUT_B
GND
PVDD_B
BST_B
GVDD_B
OCH
OCL
M1
M2
DGND
DGND
DVDD
M3
OTW
SD
RESET
GVDD_A
DVDD DREG
DREG
GVDD_A
DVDD
DREG
DREG
DREG
DREG
GVDD_B
GVDD_B
PWM
Receiver
Internally
Connected
to GVDD_x
TAS5121I
SLES122 – SEPTEMBER 2004
FUNCTIONAL BLOCK DIAGRAM
4