Datasheet
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OVERTEMPERATURE WARNING PIN: OTW
OVERALL REPORTING
CHIP PROTECTION
OVERCURRENT (OC) PROTECTION
OVERTEMPERATURE (OT) PROTECTION
UNDERVOLTAGE PROTECTION (UVP)
RESET FUNCTION
TAS5121I
SLES122 – SEPTEMBER 2004
The OTW pin gives a temperature warning signal when temperature exceeds the set limit, as shown in Table 3 .
The pin is of the open-drain type with an internal pullup to DVDD.
Table 3. OTW Temperature Indication
OTW DESCRIPTION
0 Junction temperature higher than 115 ° C
1 Junction temperature lower than 115 ° C
The SD pin, together with the OTW pin, gives chip state information as described in Table 4 .
Table 4. Error Signal Decoding
OTW SD DESCRIPTION
0 0 Overtemperature error (OTE)
0 1 Overtemperature warning (OTW)
1 0 Overcurrent (OC) or undervoltage (UVP) error
1 1 Normal operation, no errors/warnings
The TAS5121I protection function is generally implemented in a closed-loop control system with, for example, a
system controller. The TAS5121I contains three individual systems protecting the device against fault conditions.
All of the error events result in the output stage being set in a high-impedance state (Hi-Z) for maximum
protection of the device and connected equipment.
The device can be recovered by toggling RESET low and then high, after all errors are cleared. It is
recommended that if the error persists, the device is held in reset until user intervention clears the error.
The device has individual current protection on both high-side and low-side power-stage FETs. The OC
protection works only with the demodulation filter present at the output. See Filter Demodulation Design in the
Application Information section of this data sheet for design constraints.
A dual-temperature protection system asserts a warning signal when the device junction temperature exceeds
115 ° C and shuts down the device when the junction temperature exceeds 150 ° C. The OT protection circuit is
shared by both half-bridges.
Undervoltage lockout occurs when GVDD is insufficient for proper device operation. The UV protection system
protects the device under fault power-up and power-down situations by shutting the device down. The UV
protection circuits are shared by both half-bridges.
The reset has two functions:
• Reset the power stage after a latched error event.
• Hard mute—when RESET is asserted, the power stage stops switching.
In protection modes where the reset input functions as the means to re-enable operation after an error event, the
error latch is cleared on the falling edge of RESET, and normal operation is resumed on the rising edge of
RESET.
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