Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Audio amplifier 1-channel (mono) Class D HSSOP 36

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DIGITAL AMPLIFIER POWER STAGE

FEATURES

DESCRIPTION

APPLICATIONS

PVDD_X − H-Bridge Voltage − V

0 4 8 12 16 20 24 28 32

− Output Power − W

6 Ω

4 Ω

8 Ω

P − Power − W

= 4 Ω

= 75°C

Gain = 3 dB

THD+N − Total Harmonic Distortion + Noise − %

0.1 1 10 100

0.01

0.1

4 Ω

6 Ω

8 Ω

G001

TAS5121I

SLES122 – SEPTEMBER 2004

• Mini/Micro Component Systems

• Internet Music Appliance

• 100-W RMS Power (BTL) Into 4 Ω With Less

Than 10% THD+N

• 80-W RMS Power (BTL) Into 4 Ω With Less

Than 0.2% THD+N

The TAS5121I is a high-performance, digital-amplifier

power stage designed to drive a 4- Ω speaker up to

• 0.09% THD+N at 1 W Into 4 Ω

100 W. The TAS5121I is rated for operation at

• Power Stage Efficiency Greater Than 90% Into

industrial temperatures. The device incorporates

4- Ω Load

PurePath Digital™ technology and can be used with

• Self-Protecting Design

a TI audio pulse-width modulation (PWM) processor

and a simple passive demodulation filter to deliver

• Industrial Temperature Rating

high-quality, high-efficiency, digital-audio amplifi-

• 36-Pin PSOP3 Package

cation.

• 3.3-V Digital Interface

The efficiency of this digital amplifier can be greater

• EMI Compliant When Used With

than 90%, depending on the system design.

Recommended System Design

Overcurrent protection, overtemperature protection,

and undervoltage protection are built into the

TAS5121I, safeguarding the device and speakers

against fault conditions that could damage the sys-

• DVD Receiver

tem.

• Home Theatre

TOTAL HARMONIC DISTORTION + NOISE UNCLIPPED OUTPUT POWER

vs vs

POWER H-BRIDGE VOLTAGE

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PurePath Digital, PowerPAD are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (23 pages)

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TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 TM DIGITAL AMPLIFIER POWER STAGE FEATURES • 100-W RMS Power (BTL) Into 4 Ω With Less Than 10% THD+N 80-W RMS Power (BTL) Into 4 Ω With Less Than 0.2% THD+N 0.09% THD+N at 1 W Into 4 Ω Power Stage Efficiency Greater Than 90% Into 4-Ω Load Self-Protecting Design Industrial Temperature Rating 36-Pin PSOP3 Package 3.
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TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. GENERAL INFOMATION Terminal Assignment The TAS5121I is offered in a thermally enhanced 36-pin PSOP3 (DKD) package. The DKD package has the thermal pad on top.
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TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 ORDERING INFORMATION TA PACKAGE TRANSPORT MEDIA DESCRIPTION –40°C to 85°C TAS5121IDKD Tube 36-pin PSOP3 –40°C to 85°C TAS5121IDKDR Tape and reel 36-pin PSOP3 PACKAGE DISSIPATION RATINGS (1) PACKAGE RθJC (°C/W) 36-Pin DKD PSOP3 0.85 RθJA (°C/W) See (1) The TAS5121I package is thermally enhanced for conductive cooling using an exposed metal pad area.
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TAS5121I www.ti.
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TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 RECOMMENDED OPERATING CONDITIONS DVDD Digital supply (1) Relative to DGND GVDD_x Supply for internal gate drive and logic regulators Relative to GND PVDD_x Half-bridge supply Relative to GND, RL= 4 Ω TJ Junction temperature (1) MIN NOM MAX UNIT 3 3.3 3.6 V 10.8 12 13.2 V 0 30.5 0 32 V 125 °C It is recommended for DVDD to be connected to DREG via a 100-Ω resistor. ELECTRICAL CHARACTERISTICS PVDD_X = 30.
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TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) PVDD_X = 30.
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TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 TOTAL HARMONIC DISTORTION + NOISE vs POWER 90 RL = 4 Ω TC = 75°C Gain = 3 dB 80 4Ω 70 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 UNCLIPPED OUTPUT POWER vs H-BRIDGE VOLTAGE 1 6Ω 0.1 4Ω 60 6Ω 50 40 30 20 8Ω 10 8Ω 0 0.01 0.1 1 10 0 100 4 P − Power − W 8 12 16 20 24 28 32 PVDD_X − H-Bridge Voltage − V G001 Figure 1. Figure 2.
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TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 EFFICIENCY vs TOTAL OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 100 THD+N − Total Harmonic Distortion + Noise − % 10 90 80 η − Efficiency − % 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 RL = 4 Ω TC = 75°C 1 75 W 0.1 10 W 1W 0.01 20 80 100 PO(Total) − Total Output Power − W Figure 5. Figure 6. AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 PO = 1 W TC = 75°C −20 0.3 8Ω −40 0.
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TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 THEORY OF OPERATION POWER SUPPLIES This power device requires only two power supply voltages: GVDD_x and PVDD_x. GVDD_x is the gate drive supply for the device, which is usually supplied from an external 12-V power supply. GVDD_x is also connected to an internal LDR that regulates the GVDD_x voltage down to the logic power supply, 3.3 V, for the TAS5121I internal logic blocks. Each GVDD_x pin is decoupled to system ground by a 1-µF capacitor.
PAGE 10
TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 THEORY OF OPERATION (continued) low-side MOSFET in the A half-bridge is not conducting. Because the source of the high-side MOSFET is referenced to the drain of the low-side MOSFET, a bootstrapped capacitor is used to eliminate the need for additional high-voltage power supplies. Under this condition, the opposite is true for the B half-bridge of the output H-bridge.
PAGE 11
TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 OVERTEMPERATURE WARNING PIN: OTW The OTW pin gives a temperature warning signal when temperature exceeds the set limit, as shown in Table 3. The pin is of the open-drain type with an internal pullup to DVDD. Table 3. OTW Temperature Indication OTW DESCRIPTION 0 Junction temperature higher than 115°C 1 Junction temperature lower than 115°C OVERALL REPORTING The SD pin, together with the OTW pin, gives chip state information as described in Table 4.
PAGE 12
TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 PROTECTION MODE LATCHED SHUTDOWN ON ALL ERRORS In latched shutdown mode, all error situations result in a permanent shutdown (output stage Hi-Z). Re-enabling can be done by toggling the RESET pin. MODE PINS SELECTION The protection mode is selected by connecting M1/M2 to DREG or DGND according to Table 5. Table 5.
PAGE 13
TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 APPLICATION INFORMATION DEMODULATION FILTER DESIGN The TAS5121I amplifier outputs are driven by high-current DMOS transistors in an H-bridge configuration. These transistors are either off or fully on. The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio signal. It is recommended that a second-order LC filter be used to recover the audio signal.
PAGE 14
TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 APPLICATION INFORMATION (continued) INDUCTANCE vs CURRENT 11 DBF1310A 10 L − Inductance − µH 9 DASL983XX−1023 8 7 6 5 4 0 5 10 15 I − Current − A Figure 10. Inductance Saturation The selection of the capacitors that are placed from the output of each inductor to ground is simple. To complete the output filter, use a 1-µF capacitor with a voltage rating at least twice the voltage applied to the output stage (PVDD_x).
PAGE 15
TAS5121I www.ti.com SLES122 – SEPTEMBER 2004 APPLICATION INFORMATION (continued) 36-pin PSOP3 0.47 °C/W The thermal resistance of thermally conductive pads is generally higher than a thin thermal grease layer. Thermal tape has an even higher thermal resistance and should not be used with this package. Heatsink thermal resistance is generally predicted by the heatsink vendor, modeled using a continuous flow dynamics (CFD) model, or measured.
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 18
PACKAGE MATERIALS INFORMATION www.ti.com 12-Jun-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS5121IDKDR Package Package Pins Type Drawing SPQ HSSOP 500 DKD 36 Reel Reel Diameter Width (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 14.7 16.4 4.0 20.0 24.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 12-Jun-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5121IDKDR HSSOP DKD 36 500 337.0 343.0 41.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.