Datasheet

TAS5112A
SLES094B - OCTOBER 2003 - REVISED JUNE 2008
www.ti.com
2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
Terminal Assignment
The TAS5112A is offered in a thermally enhanced 56-pin
TSSOP DFD (thermal pad is on the top) and DCA (thermal
pad is on the bottom), shown as follows.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
GND
GREG
OTW
SD_CD
SD_AB
PWM_DP
PWM_DM
RESET_CD
PWM_CM
PWM_CP
DREG_RTN
M3
M2
M1
DREG
PWM_BP
PWM_BM
RESET_AB
PWM_AM
PWM_AP
GND
DGND
GND
DVDD
GREG
GND
GND
GND
GVDD
BST_D
PVDD_
D
PVDD_
D
OUT_D
OUT_D
GND
GND
OUT_C
OUT_C
PVDD_
C
PVDD_
C
BST_C
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND
GND
OUT_A
OUT_A
PVDD_A
PVDD_A
BST_A
GVDD
GND
DFD PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
GND
GREG
DVDD
GND
DGND
GND
PWM_AP
PWM_AM
RESET_AB
PWM_BM
PWM_BP
DREG
M1
M2
M3
DREG_RTN
PWM_CP
PWM_CM
RESET_CD
PWM_DM
PWM_DP
SD_AB
SD_CD
OTW
GREG
GND
GND
GND
GVDD
BST_A
PVDD_A
PVDD_A
OUT_A
OUT_A
GND
GND
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_
C
PVDD_
C
OUT_C
OUT_C
GND
GND
OUT_D
OUT_D
PVDD_
D
PVDD_
D
BST_D
GVDD
GND
DCA PACKAGE
(TOP VIEW)