Datasheet
Serial Audio Port
t
h1
t
su1
t
su2
t
h2
SCLK
(Input)
LRCLK
(Input)
SDIN1
SDIN2
SDIN3
T0026-01
TAS5086 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I
2
C-Bus
TAS5086
www.ti.com
................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008
Serial audio port slave mode over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCLKIN
SCLK input frequency C
L
= 30 pF, SCLK = 64 f
S
2.048 12.288 MHz
t
su1
Setup time, LRCLK to SCLK rising edge 10 ns
t
h1
Hold time, LRCLK from SCLK rising edge 10 ns
t
su2
Setup time, SDIN to SCLK rising edge 10 ns
t
h2
Hold time, SDIN from SCLK rising edge 10 ns
LRCLK frequency 32 48 192 kHz
SCLK duty cycle 40% 50% 60%
LRCLK duty cycle 40% 50% 60%
SCLK
SCLK rising edges between LRCLK rising edges 64 64
edges
LRCLK clock edge with respect to the falling edge of SCLK
– 1/4 1/4
SCLK period
Figure 2. Slave Mode Serial Data Interface Timing
Devices
STANDARD MODE FAST MODE
PARAMETER TEST CONDITIONS UNIT
MIN MAX MIN MAX
V
IL
LOW-level input voltage – 0.5 0.3 V
DD
– 0.5 0.3 V
DD
V
V
IH
HIGH-level input voltage 0.7 V
DD
0.7 V
DD
V
V
hys
Hysteresis of Schmitt-trigger inputs N/A N/A 0.05 V
DD
V
LOW-level output voltage (open drain or
V
OL1
3-mA sink current 0 0.4 V
open collector)
Bus capacitance from 10 pF 7 + 0.1 C
b
t
of
Output fall time from V
IHmin
to
VILmax
250 250 ns
to 400 pF
(1)
t
SP
Pulse duration of spikes suppressed
(2)
N/A N/A 0 30 ns
I
i
Input current, each I/O pin – 30 30 – 30
(3)
30
(3)
µ A
C
i
Capacitance, each I/O pin 10 10 pF
(1) C
b
= capacitance of one bus line in pF. The output fall time is faster than the standard I
2
C specification.
(2) SCL and SDA have a 30-ns glitch filter.
(3) The I/O pins of fast-mode devices must not obstruct the SDA and SDL lines if V
DD
is switched off.
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