Datasheet

SERIAL DATA INTERFACE
I
2
C SERIAL CONTROL INTERFACE
B0048-01
(L'+R')/2
Format
Channel
1–6
Channel
1–6
1–5
1–5
Down-
mix
SDIN1
PWM_1
PWM_2
PWM_3
PWM_4
PWM_5
PWM_6
1LF
2RF
3LS
4RS
5C
0x20
0x21
0x25
L'
R'
L'
R'
0x04
SDIN2
SDIN3
SDIN4
SDIN4
MUX
0x21
Ch-6Processing
MUX
MUX
Downmix
SDIN4
PWM
MUX
SDOUT
I S
2
0x07– 0x0D
0x03
VOL
SEL
VOL
VOL
VOL
VOL
MUX
TAS5086
www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008
Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The PWM outputs and downmix are derived from
SDIN1, SDIN2, and SDIN3. SDIN4 is a selectable pass-through signal that is available at SDOUT as an I
2
S
output. The TAS5086 accepts 32-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz serial data in 16-, 20-, or 24-bit,
left-justified, right-justified, and I
2
S serial data formats.
Serial data is output on SDOUT. The SDOUT data format is I
2
S 24-bit at the same data rate as the input. The
SDOUT output is synchronized to use the SCLK and LRCLK signals. There is a 1- to 2.5-LRCLK frame delay
from the input data to the output data, depending on the input serial data format. The SDOUT output has no
I
2
C-controllable functions. It is always operational.
The parameters of this clock and serial data interface input format are I
2
C configurable.
The TAS5086 has an I
2
C serial control slave interface to receive commands from a system controller. The serial
control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait states.
As an added feature, this interface operates even if MCLK is absent.
The serial control interface supports both single-byte and multi-byte read and write operations for status registers
and the general control registers associated with the PWM.
The I
2
C interface supports a special mode that permits I
2
C write operations to be broken up into multiple-data
write operations that are multiples of 4 data bytes. These are 6-, 10-, 14-, 18-, ... etc., -byte write operations that
are composed of a device address, read/write bit, subaddress, and any multiple of 4 bytes of data. This permits
the system to write large register values incrementally without blocking other I
2
C transactions.
Figure 6 shows the data flow and control through the TAS5086. The major I
2
C registers are shown above each
applicable block (e.g., 0x04 is the serial data format control register).
Figure 6. TAS5086 Data Flow Diagram With I
2
C Registers
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