Datasheet
TAS5086 Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I
2
C-Bus
SDA
SCL
t
f
t
SU-DAT
t
HD-STA
t
r
t
BUF
t
SU-STO
P S
t
SP
t
SU-STA
Sr
t
HIGH
t
HD-DAT
t
LOW
t
r
t
HD-STA
S
t
f
T0114-01
TAS5086
SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ...................................................................................................................................................
www.ti.com
Devices
All values are referred to V
IHmin
and V
ILmax
(see TAS5086 Pin-Related Characteristics of the SDA and SCL I/O Stages for
F/S-Mode I2C-Bus Devices ).
A
STANDARD MODE FAST MODE
PARAMETER TEST CONDITIONS UNIT
MIN MAX MIN MAX
f
SCL
SCL clock frequency 0 100 0 400 kHz
Hold time (repeated) START condition.
t
HD-STA
After this period, the first clock pulse is 4 0.6 µ s
generated.
t
LOW
LOW period of the SCL clock 4.7 1.3 µ s
t
HIGH
HIGH period of the SCL clock 4 0.6 µ s
t
SU-STA
Setup time for repeated START 4.7 0.6 µ s
t
SU-DAT
Data setup time 250 100 µ s
t
HD-DAT
Data hold time
(1) (2)
0 3.45 0 0.9 µ s
t
r
Rise time of both SDA and SCL 1000 7 + 0.1 C
b
(3)
500
(4)
ns
t
f
Fall time of both SDA and SCL 300 7 + 0.1 C
b
(3)
300 ns
t
SU-STO
Setup time for STOP condition 4 0.6 µ s
t
BUF
Bus free time between a STOP and 4.7 1.3 µ s
START condition
C
b
Capacitive loads for each bus line 400 400 pF
Noise margin at the LOW level for each
V
nL
0.1 V
DD
0.1 V
DD
V
connected device (including hysteresis)
Noise margin at the HIGH level for each
V
nH
0.2 V
DD
0.2 V
DD
V
connected device (including hysteresis)
(1) Note that SDA does not have the standard I
2
C specification 300-ns hold time and that SDA must be valid by the rising and falling edges
of SCL. TI recommends that a 3.3-k Ω pullup resistor be used to avoid potential timing issues.
(2) A fast-mode I
2
C-bus device can be used in a standard-mode I
2
C-bus system, but the requirement t
SU-DAT
≥ 250 ns must then be met.
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
r-max
+ t
SU-DAT
= 1000 + 250 = 1250 ns (according to the
standard-mode I
2
C bus specification) before the SCL line is released.
(3) C
b
= total capacitance of one bus line in pF.
(4) Rise time varies with pullup resistor.
Figure 3. Start and Stop Conditions Timing Waveforms
6 Submit Documentation Feedback Copyright © 2005 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TAS5086