Datasheet

OSCILLATOR TRIM REGISTER (0x1B)
Oscillator Factory-Trim Enable Procedure Example
Oscillator Field-Trim Procedure Example (Use only if input LRCLK frequency is known)
BKNDERR REGISTER (0x1C)
TAS5086
www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008
The TAS5086 PWM processor contains an internal oscillator for PLL reference. This reduces system cost
because an external reference is not required. A trim resitor value of 18 k Ω is recomended. This should be
connected between TAS5086 pin 14 (OSC_RES) and pin 12 (DVSS).
Two procedures are available for trimming the internal oscillator. The factory-trim procedure is recommended for
most users. This procedure simply enables the factory trim that was previously done at the TAS5086 factory.
Note that only one trim procedure should be used. It always should be run following reset of the TAS5086.
1. Reset the TAS5086 (power up or toggle the RESET pin).
2. Write data 0x00 to register 0x1B (enable factory trim).
3. Write data 0x20 to register 0x05 (start all channels).
4. Write data 0x30 to register 0x07 (unmute and set master volume to 0 dB).
1. Reset the TAS5086 (power up or toggle the RESET pin).
2. Provide a known LRCLK (e.g., 48 kHz).
3. Write LRCLK frequency to register 0x00 (e.g., for 48 kHz, write 0x6D to register 0x00).
4. Write data 0x03 to register 0x1B (field-trim command).
5. Write data 0x20 to register 0x05 (start all channels).
6. Write data 0x30 to register 0x07 (unmute and set master volume to 0 dB).
Table 15. Oscillator Trim Register (0x1B)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
– 0 – – – – – – Oscillator trim not done (read only)
– 1 – – – – – – Oscillator trim done
– – 0 0 0 0 – – Reserved
– – – – – – 0 – Select factory trim
– – – – – – 1 – Select field trim
– – – – – – – 1 Trim oscillator command
When a back-end error signal is received ( BKND_ERR = LOW), all the output stages are reset by setting all
PWM, VALID1, and VALID2 signals LOW. Subsequently, the modulator waits approximately for the time listed in
Table 16 before initiation of a reset.
Table 16. BKNDERR Register (0x1C)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
– – – – 0 0 0 0 Set back-end reset period to < 1.3 ms
– – – – 0 0 0 1 Set back-end reset period to 1.3 ms
– – – – 0 0 1 0 Set back-end reset period to 2.6 ms
– – – – 0 0 1 1 Set back-end reset period to 3.9 ms
– – – – 0 1 0 0 Set back-end reset period to 5.2 ms
– – – – 0 1 0 1 Set back-end reset period to 6.5 ms
– – – – 0 1 1 0 Set back-end reset period to 7.8 ms
– – – – 0 1 1 1 Set back-end reset period to 9.1 ms
– – – – 1 0 0 0 Set back-end reset period to 10.4 ms
– – – – 1 0 0 1 Set back-end reset period to 11.7 ms
– – – – 1 0 1 0 Set back-end reset period to 13 ms
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